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vkd3d-shader: Add basic support for dcl_index_range.
We can address SPIR-V arrays dynamically. Signed-off-by: Józef Kucia <jkucia@codeweavers.com> Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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@ -619,8 +619,8 @@ static void shader_sm4_read_dcl_index_range(struct vkd3d_shader_instruction *ins
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struct vkd3d_sm4_data *priv)
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struct vkd3d_sm4_data *priv)
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{
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{
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shader_sm4_read_dst_param(priv, &tokens, &tokens[token_count], VKD3D_DATA_OPAQUE,
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shader_sm4_read_dst_param(priv, &tokens, &tokens[token_count], VKD3D_DATA_OPAQUE,
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&ins->declaration.index_range.first_register);
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&ins->declaration.index_range.dst);
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ins->declaration.index_range.last_register = *tokens;
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ins->declaration.index_range.register_count = *tokens;
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}
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}
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static void shader_sm4_read_dcl_output_topology(struct vkd3d_shader_instruction *ins,
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static void shader_sm4_read_dcl_output_topology(struct vkd3d_shader_instruction *ins,
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@ -2568,14 +2568,17 @@ static void vkd3d_dxbc_compiler_emit_dereference_register(struct vkd3d_dxbc_comp
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}
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}
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else if (register_info->is_aggregate)
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else if (register_info->is_aggregate)
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{
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{
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if (reg->idx[0].rel_addr || reg->idx[1].rel_addr)
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if (reg->idx[1].rel_addr)
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FIXME("Relative addressing not implemented.\n");
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FIXME("Relative addressing not implemented.\n");
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if (reg->idx[0].rel_addr)
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indexes[index_count++] = vkd3d_dxbc_compiler_emit_register_addressing(compiler, ®->idx[0]);
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else
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indexes[index_count++] = vkd3d_dxbc_compiler_get_constant_uint(compiler, register_info->member_idx);
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indexes[index_count++] = vkd3d_dxbc_compiler_get_constant_uint(compiler, register_info->member_idx);
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}
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}
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else
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else
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{
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{
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if (reg->idx[1].rel_addr)
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if (reg->idx[1].rel_addr || (reg->idx[1].offset == ~0u && reg->idx[0].rel_addr))
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FIXME("Relative addressing not implemented.\n");
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FIXME("Relative addressing not implemented.\n");
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/* Handle arrayed registers, e.g. v[3][0]. */
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/* Handle arrayed registers, e.g. v[3][0]. */
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@ -4754,6 +4757,64 @@ static void vkd3d_dxbc_compiler_emit_dcl_output_siv(struct vkd3d_dxbc_compiler *
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vkd3d_dxbc_compiler_emit_output(compiler, dst, sysval);
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vkd3d_dxbc_compiler_emit_output(compiler, dst, sysval);
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}
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}
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static bool vkd3d_dxbc_compiler_check_index_range(struct vkd3d_dxbc_compiler *compiler,
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const struct vkd3d_shader_index_range *range)
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{
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const struct vkd3d_shader_register *reg = &range->dst.reg;
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struct vkd3d_shader_register_info reg_info;
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struct vkd3d_shader_register current_reg;
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struct vkd3d_symbol reg_symbol;
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unsigned int i;
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uint32_t id;
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current_reg = *reg;
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vkd3d_symbol_make_register(®_symbol, ¤t_reg);
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if (!vkd3d_dxbc_compiler_get_register_info(compiler, ¤t_reg, ®_info))
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{
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ERR("Failed to get register info.\n");
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return false;
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}
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/* FIXME: We should check if it's an array. */
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if (!reg_info.is_aggregate)
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{
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FIXME("Unhandled register %#x.\n", reg->type);
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return false;
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}
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id = reg_info.id;
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for (i = reg->idx[0].offset; i < reg->idx[0].offset + range->register_count; ++i)
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{
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current_reg.idx[0].offset = i;
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vkd3d_symbol_make_register(®_symbol, ¤t_reg);
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if (range->dst.write_mask != reg_info.write_mask
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|| vkd3d_write_mask_component_count(reg_info.write_mask) != 1)
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{
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FIXME("Unhandled index range write mask %#x (%#x).\n",
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range->dst.write_mask, reg_info.write_mask);
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return false;
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}
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if (reg_info.id != id)
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{
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FIXME("Unhandled index range %#x, %u.\n", reg->type, i);
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return false;
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}
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}
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return true;
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}
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static void vkd3d_dxbc_compiler_emit_dcl_index_range(struct vkd3d_dxbc_compiler *compiler,
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const struct vkd3d_shader_instruction *instruction)
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{
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const struct vkd3d_shader_index_range *range = &instruction->declaration.index_range;
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if (!vkd3d_dxbc_compiler_check_index_range(compiler, range))
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FIXME("Ignoring dcl_index_range %#x %u.\n", range->dst.reg.type, range->register_count);
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}
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static void vkd3d_dxbc_compiler_emit_dcl_stream(struct vkd3d_dxbc_compiler *compiler,
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static void vkd3d_dxbc_compiler_emit_dcl_stream(struct vkd3d_dxbc_compiler *compiler,
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const struct vkd3d_shader_instruction *instruction)
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const struct vkd3d_shader_instruction *instruction)
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{
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{
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@ -7388,6 +7449,9 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
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case VKD3DSIH_DCL_OUTPUT_SIV:
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case VKD3DSIH_DCL_OUTPUT_SIV:
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vkd3d_dxbc_compiler_emit_dcl_output_siv(compiler, instruction);
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vkd3d_dxbc_compiler_emit_dcl_output_siv(compiler, instruction);
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break;
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break;
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case VKD3DSIH_DCL_INDEX_RANGE:
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vkd3d_dxbc_compiler_emit_dcl_index_range(compiler, instruction);
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break;
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case VKD3DSIH_DCL_STREAM:
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case VKD3DSIH_DCL_STREAM:
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vkd3d_dxbc_compiler_emit_dcl_stream(compiler, instruction);
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vkd3d_dxbc_compiler_emit_dcl_stream(compiler, instruction);
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break;
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break;
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@ -7730,7 +7794,6 @@ static void vkd3d_dxbc_compiler_emit_shader_epilogue_function(struct vkd3d_dxbc_
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vkd3d_spirv_build_op_function(builder, void_id, function_id,
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vkd3d_spirv_build_op_function(builder, void_id, function_id,
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SpvFunctionControlMaskNone, function_type_id);
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SpvFunctionControlMaskNone, function_type_id);
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vkd3d_spirv_build_op_name(builder, function_id, "epilogue");
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for (i = 0; i < ARRAY_SIZE(compiler->private_output_variable); ++i)
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for (i = 0; i < ARRAY_SIZE(compiler->private_output_variable); ++i)
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{
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{
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@ -7789,7 +7852,10 @@ int vkd3d_dxbc_compiler_generate_spirv(struct vkd3d_dxbc_compiler *compiler,
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}
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}
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if (compiler->epilogue_function_id)
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if (compiler->epilogue_function_id)
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{
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vkd3d_spirv_build_op_name(builder, compiler->epilogue_function_id, "epilogue");
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vkd3d_dxbc_compiler_emit_shader_epilogue_function(compiler);
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vkd3d_dxbc_compiler_emit_shader_epilogue_function(compiler);
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}
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if (compiler->options & VKD3D_SHADER_STRIP_DEBUG)
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if (compiler->options & VKD3D_SHADER_STRIP_DEBUG)
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vkd3d_spirv_stream_clear(&builder->debug_stream);
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vkd3d_spirv_stream_clear(&builder->debug_stream);
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@ -1389,8 +1389,8 @@ static void shader_dump_instruction(struct vkd3d_string_buffer *buffer,
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case VKD3DSIH_DCL_INDEX_RANGE:
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case VKD3DSIH_DCL_INDEX_RANGE:
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shader_addline(buffer, "%s ", shader_opcode_names[ins->handler_idx]);
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shader_addline(buffer, "%s ", shader_opcode_names[ins->handler_idx]);
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shader_dump_dst_param(buffer, &ins->declaration.index_range.first_register, shader_version);
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shader_dump_dst_param(buffer, &ins->declaration.index_range.dst, shader_version);
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shader_addline(buffer, " %u", ins->declaration.index_range.last_register);
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shader_addline(buffer, " %u", ins->declaration.index_range.register_count);
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break;
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break;
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case VKD3DSIH_DCL_INDEXABLE_TEMP:
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case VKD3DSIH_DCL_INDEXABLE_TEMP:
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@ -584,8 +584,8 @@ struct vkd3d_shader_src_param
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struct vkd3d_shader_index_range
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struct vkd3d_shader_index_range
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{
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{
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struct vkd3d_shader_dst_param first_register;
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struct vkd3d_shader_dst_param dst;
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unsigned int last_register;
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unsigned int register_count;
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};
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};
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enum vkd3d_decl_usage
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enum vkd3d_decl_usage
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