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vkd3d-shader/hlsl: Use VKD3DSPR_COMBINED_SAMPLER destination operands in sm1_generate_vsir_sampler_dcls().

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That's what the d3d-asm target expects in shader_print_dcl_usage(), and
what vkd3d_shader_scan() requires to create correct descriptor
information.
This commit is contained in:
Henri Verbeet
2025-09-09 19:11:16 +02:00
parent 4569a9d5ba
commit 84d3a8d167
Notes: Henri Verbeet 2025-09-11 16:15:21 +02:00 
Approved-by: Francisco Casas (@fcasas)
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1724
2 changed files with 2 additions and 2 deletions
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2
libs/vkd3d-shader/d3dbc.c
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@@ -1954,7 +1954,7 @@ static void d3dbc_write_vsir_dcl(struct d3dbc_compiler *d3dbc, const struct vkd3
reg_id = semantic->resource.reg.reg.idx[0].offset; reg_id = semantic->resource.reg.reg.idx[0].offset;
if (semantic->resource.reg.reg.type != VKD3DSPR_SAMPLER) if (semantic->resource.reg.reg.type != VKD3DSPR_COMBINED_SAMPLER)
{ {
vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_TYPE, vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_TYPE,
"dcl instruction with register type %u.", semantic->resource.reg.reg.type); "dcl instruction with register type %u.", semantic->resource.reg.reg.type);

2
libs/vkd3d-shader/hlsl_codegen.c
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@@ -8949,7 +8949,7 @@ static void sm1_generate_vsir_sampler_dcls(struct hlsl_ctx *ctx,
semantic->resource_type = resource_type; semantic->resource_type = resource_type;
dst_param = &semantic->resource.reg; dst_param = &semantic->resource.reg;
vsir_register_init(&dst_param->reg, VKD3DSPR_SAMPLER, VSIR_DATA_F32, 1); vsir_register_init(&dst_param->reg, VKD3DSPR_COMBINED_SAMPLER, VSIR_DATA_F32, 1);
dst_param->reg.dimension = VSIR_DIMENSION_NONE; dst_param->reg.dimension = VSIR_DIMENSION_NONE;
dst_param->reg.idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].index + i; dst_param->reg.idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].index + i;
dst_param->write_mask = 0; dst_param->write_mask = 0;