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vkd3d-shader/hlsl: Save simple hlsl_ir_exprs in the vsir_program for SM1.
This commit is contained in:
Francisco Casas
committed by
Henri Verbeet
Henri Verbeet
parent
f6a8cdf2bb
commit
82dec5db46
Notes:
Henri Verbeet
2024-09-11 15:33:53 +02:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1041
@ -1987,63 +1987,6 @@ static void d3dbc_write_dp2add(struct d3dbc_compiler *d3dbc, const struct hlsl_r
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d3dbc_write_instruction(d3dbc, &instr);
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}
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static void d3dbc_write_ternary_op(struct d3dbc_compiler *d3dbc, enum vkd3d_sm1_opcode opcode,
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const struct hlsl_reg *dst, const struct hlsl_reg *src1,
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const struct hlsl_reg *src2, const struct hlsl_reg *src3)
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{
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struct sm1_instruction instr =
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{
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.opcode = opcode,
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.dst.type = VKD3DSPR_TEMP,
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.dst.writemask = dst->writemask,
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.dst.reg = dst->id,
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.has_dst = 1,
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.srcs[0].type = VKD3DSPR_TEMP,
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.srcs[0].swizzle = hlsl_swizzle_from_writemask(src1->writemask),
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.srcs[0].reg = src1->id,
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.srcs[1].type = VKD3DSPR_TEMP,
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.srcs[1].swizzle = hlsl_swizzle_from_writemask(src2->writemask),
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.srcs[1].reg = src2->id,
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.srcs[2].type = VKD3DSPR_TEMP,
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.srcs[2].swizzle = hlsl_swizzle_from_writemask(src3->writemask),
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.srcs[2].reg = src3->id,
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.src_count = 3,
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};
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sm1_map_src_swizzle(&instr.srcs[0], instr.dst.writemask);
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sm1_map_src_swizzle(&instr.srcs[1], instr.dst.writemask);
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sm1_map_src_swizzle(&instr.srcs[2], instr.dst.writemask);
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d3dbc_write_instruction(d3dbc, &instr);
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}
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static void d3dbc_write_binary_op(struct d3dbc_compiler *d3dbc, enum vkd3d_sm1_opcode opcode,
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const struct hlsl_reg *dst, const struct hlsl_reg *src1, const struct hlsl_reg *src2)
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{
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struct sm1_instruction instr =
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{
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.opcode = opcode,
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.dst.type = VKD3DSPR_TEMP,
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.dst.writemask = dst->writemask,
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.dst.reg = dst->id,
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.has_dst = 1,
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.srcs[0].type = VKD3DSPR_TEMP,
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.srcs[0].swizzle = hlsl_swizzle_from_writemask(src1->writemask),
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.srcs[0].reg = src1->id,
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.srcs[1].type = VKD3DSPR_TEMP,
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.srcs[1].swizzle = hlsl_swizzle_from_writemask(src2->writemask),
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.srcs[1].reg = src2->id,
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.src_count = 2,
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};
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sm1_map_src_swizzle(&instr.srcs[0], instr.dst.writemask);
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sm1_map_src_swizzle(&instr.srcs[1], instr.dst.writemask);
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d3dbc_write_instruction(d3dbc, &instr);
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}
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static void d3dbc_write_dot(struct d3dbc_compiler *d3dbc, enum vkd3d_sm1_opcode opcode,
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const struct hlsl_reg *dst, const struct hlsl_reg *src1, const struct hlsl_reg *src2)
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{
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@ -2332,7 +2275,13 @@ static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
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const struct vkd3d_sm1_opcode_info *info;
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struct sm1_instruction instr = {0};
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info = shader_sm1_get_opcode_info_from_vsir(d3dbc, ins->opcode);
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if (!(info = shader_sm1_get_opcode_info_from_vsir(d3dbc, ins->opcode)))
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{
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vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_OPCODE,
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"Opcode %#x not supported for shader profile.", ins->opcode);
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d3dbc->failed = true;
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return;
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}
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if (ins->dst_count != info->dst_count)
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{
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@ -2375,7 +2324,18 @@ static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const str
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d3dbc_write_vsir_dcl(d3dbc, ins);
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break;
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case VKD3DSIH_ABS:
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case VKD3DSIH_ADD:
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case VKD3DSIH_CMP:
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case VKD3DSIH_DSX:
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case VKD3DSIH_DSY:
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case VKD3DSIH_FRC:
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case VKD3DSIH_MAD:
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case VKD3DSIH_MAX:
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case VKD3DSIH_MIN:
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case VKD3DSIH_MOV:
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case VKD3DSIH_MUL:
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case VKD3DSIH_SLT:
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d3dbc_write_vsir_simple_instruction(d3dbc, ins);
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break;
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@ -2510,7 +2470,6 @@ static void d3dbc_write_sincos(struct d3dbc_compiler *d3dbc, enum hlsl_ir_expr_o
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static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_node *instr)
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{
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const struct vkd3d_shader_version *version = &d3dbc->program->shader_version;
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struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
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struct hlsl_ir_node *arg1 = expr->operands[0].node;
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struct hlsl_ir_node *arg2 = expr->operands[1].node;
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@ -2540,18 +2499,6 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
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switch (expr->op)
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{
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case HLSL_OP1_ABS:
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d3dbc_write_unary_op(d3dbc, VKD3D_SM1_OP_ABS, &instr->reg, &arg1->reg, 0, 0);
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break;
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case HLSL_OP1_DSX:
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d3dbc_write_unary_op(d3dbc, VKD3D_SM1_OP_DSX, &instr->reg, &arg1->reg, 0, 0);
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break;
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case HLSL_OP1_DSY:
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d3dbc_write_unary_op(d3dbc, VKD3D_SM1_OP_DSY, &instr->reg, &arg1->reg, 0, 0);
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break;
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case HLSL_OP1_EXP2:
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d3dbc_write_per_component_unary_op(d3dbc, instr, VKD3D_SM1_OP_EXP);
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break;
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@ -2560,14 +2507,6 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
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d3dbc_write_per_component_unary_op(d3dbc, instr, VKD3D_SM1_OP_LOG);
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break;
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case HLSL_OP1_NEG:
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d3dbc_write_unary_op(d3dbc, VKD3D_SM1_OP_MOV, &instr->reg, &arg1->reg, D3DSPSM_NEG, 0);
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break;
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case HLSL_OP1_SAT:
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d3dbc_write_unary_op(d3dbc, VKD3D_SM1_OP_MOV, &instr->reg, &arg1->reg, 0, D3DSPDM_SATURATE);
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break;
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case HLSL_OP1_RCP:
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d3dbc_write_per_component_unary_op(d3dbc, instr, VKD3D_SM1_OP_RCP);
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break;
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@ -2581,26 +2520,6 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
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d3dbc_write_sincos(d3dbc, expr->op, &instr->reg, &arg1->reg);
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break;
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case HLSL_OP2_ADD:
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d3dbc_write_binary_op(d3dbc, VKD3D_SM1_OP_ADD, &instr->reg, &arg1->reg, &arg2->reg);
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break;
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case HLSL_OP2_MAX:
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d3dbc_write_binary_op(d3dbc, VKD3D_SM1_OP_MAX, &instr->reg, &arg1->reg, &arg2->reg);
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break;
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case HLSL_OP2_MIN:
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d3dbc_write_binary_op(d3dbc, VKD3D_SM1_OP_MIN, &instr->reg, &arg1->reg, &arg2->reg);
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break;
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case HLSL_OP2_MUL:
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d3dbc_write_binary_op(d3dbc, VKD3D_SM1_OP_MUL, &instr->reg, &arg1->reg, &arg2->reg);
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break;
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case HLSL_OP1_FRACT:
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d3dbc_write_unary_op(d3dbc, VKD3D_SM1_OP_FRC, &instr->reg, &arg1->reg, D3DSPSM_NONE, 0);
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break;
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case HLSL_OP2_DOT:
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switch (arg1->data_type->dimx)
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{
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@ -2617,34 +2536,10 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
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}
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break;
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case HLSL_OP2_LOGIC_AND:
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d3dbc_write_binary_op(d3dbc, VKD3D_SM1_OP_MIN, &instr->reg, &arg1->reg, &arg2->reg);
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break;
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case HLSL_OP2_LOGIC_OR:
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d3dbc_write_binary_op(d3dbc, VKD3D_SM1_OP_MAX, &instr->reg, &arg1->reg, &arg2->reg);
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break;
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case HLSL_OP2_SLT:
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if (version->type == VKD3D_SHADER_TYPE_PIXEL)
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hlsl_fixme(ctx, &instr->loc, "Lower SLT instructions for pixel shaders.");
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d3dbc_write_binary_op(d3dbc, VKD3D_SM1_OP_SLT, &instr->reg, &arg1->reg, &arg2->reg);
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break;
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case HLSL_OP3_CMP:
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if (version->type == VKD3D_SHADER_TYPE_VERTEX)
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hlsl_fixme(ctx, &instr->loc, "Lower CMP instructions for vertex shaders.");
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d3dbc_write_ternary_op(d3dbc, VKD3D_SM1_OP_CMP, &instr->reg, &arg1->reg, &arg2->reg, &arg3->reg);
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break;
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case HLSL_OP3_DP2ADD:
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d3dbc_write_dp2add(d3dbc, &instr->reg, &arg1->reg, &arg2->reg, &arg3->reg);
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break;
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case HLSL_OP3_MAD:
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d3dbc_write_ternary_op(d3dbc, VKD3D_SM1_OP_MAD, &instr->reg, &arg1->reg, &arg2->reg, &arg3->reg);
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break;
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default:
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hlsl_fixme(ctx, &instr->loc, "SM1 \"%s\" expression.", debug_hlsl_expr_op(expr->op));
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break;
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