vkd3d-shader/hlsl: Rename hlsl_reg.bind_count to hlsl_reg.allocation_size.

We have to distinguish between the "bind count" and the "allocation size"
of variables.

The "allocation size" affects the starting register id for the resource to
be allocated next, while the "bind count" is determined by the last field
actually used. The former may be larger than the latter.

What we are currently calling hlsl_reg.bind_count is actually the
"allocation size", so a rename is in order.

The real "bind count", which will be introduced in following patches,
is important because it is what should be shown in the RDEF table and
some resource allocation rules depend on it.

For instance, for this shader:

    texture2D texs[3];
    texture2D tex;

    float4 main() : sv_target
    {
        return texs[0].Load(int3(0, 0, 0)) + tex.Load(int3(0, 0, 0));
    }

the variable "texs" has a "bind count" of 1, but an "allocation size" of
3:

    // Resource Bindings:
    //
    // Name                                 Type  Format         Dim      HLSL Bind  Count
    // ------------------------------ ---------- ------- ----------- -------------- ------
    // texs                              texture  float4          2d             t0      1
    // tex                               texture  float4          2d             t3      1
This commit is contained in:
Francisco Casas 2023-08-04 13:21:27 -04:00 committed by Alexandre Julliard
parent 948c4145f5
commit 7eba063136
Notes: Alexandre Julliard 2023-08-15 22:06:06 +02:00
Approved-by: Giovanni Mascellani (@giomasce)
Approved-by: Zebediah Figura (@zfigura)
Approved-by: Henri Verbeet (@hverbeet)
Approved-by: Alexandre Julliard (@julliard)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/299
4 changed files with 15 additions and 15 deletions

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@ -1686,7 +1686,7 @@ static void write_sm1_uniforms(struct hlsl_ctx *ctx, struct vkd3d_bytecode_buffe
else else
{ {
put_u32(buffer, vkd3d_make_u32(D3DXRS_SAMPLER, var->regs[r].id)); put_u32(buffer, vkd3d_make_u32(D3DXRS_SAMPLER, var->regs[r].id));
put_u32(buffer, var->regs[r].bind_count); put_u32(buffer, var->regs[r].allocation_size);
} }
put_u32(buffer, 0); /* type */ put_u32(buffer, 0); /* type */
put_u32(buffer, 0); /* FIXME: default value */ put_u32(buffer, 0); /* FIXME: default value */
@ -2033,7 +2033,7 @@ static void write_sm1_sampler_dcls(struct hlsl_ctx *ctx, struct vkd3d_bytecode_b
if (!var->regs[HLSL_REGSET_SAMPLERS].allocated) if (!var->regs[HLSL_REGSET_SAMPLERS].allocated)
continue; continue;
count = var->regs[HLSL_REGSET_SAMPLERS].bind_count; count = var->regs[HLSL_REGSET_SAMPLERS].allocation_size;
for (i = 0; i < count; ++i) for (i = 0; i < count; ++i)
{ {

View File

@ -257,7 +257,7 @@ struct hlsl_reg
/* Number of registers to be allocated. /* Number of registers to be allocated.
* Unlike the variable's type's regsize, it is not expressed in register components, but rather * Unlike the variable's type's regsize, it is not expressed in register components, but rather
* in whole registers, and may depend on which components are used within the shader. */ * in whole registers, and may depend on which components are used within the shader. */
uint32_t bind_count; uint32_t allocation_size;
/* For numeric registers, a writemask can be provided to indicate the reservation of only some /* For numeric registers, a writemask can be provided to indicate the reservation of only some
* of the 4 components. */ * of the 4 components. */
unsigned int writemask; unsigned int writemask;

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@ -2868,7 +2868,7 @@ static void allocate_register_reservations(struct hlsl_ctx *ctx)
continue; continue;
regset = hlsl_type_get_regset(var->data_type); regset = hlsl_type_get_regset(var->data_type);
if (var->reg_reservation.reg_type && var->regs[regset].bind_count) if (var->reg_reservation.reg_type && var->regs[regset].allocation_size)
{ {
if (var->reg_reservation.reg_type != get_regset_name(regset)) if (var->reg_reservation.reg_type != get_regset_name(regset))
{ {
@ -2886,7 +2886,7 @@ static void allocate_register_reservations(struct hlsl_ctx *ctx)
var->regs[regset].id = var->reg_reservation.reg_index; var->regs[regset].id = var->reg_reservation.reg_index;
TRACE("Allocated reserved %s to %c%u-%c%u.\n", var->name, var->reg_reservation.reg_type, TRACE("Allocated reserved %s to %c%u-%c%u.\n", var->name, var->reg_reservation.reg_type,
var->reg_reservation.reg_index, var->reg_reservation.reg_type, var->reg_reservation.reg_index, var->reg_reservation.reg_type,
var->reg_reservation.reg_index + var->regs[regset].bind_count); var->reg_reservation.reg_index + var->regs[regset].allocation_size);
} }
} }
} }
@ -3144,7 +3144,7 @@ static struct hlsl_reg allocate_register(struct hlsl_ctx *ctx, struct register_a
record_allocation(ctx, allocator, reg_idx, writemask, first_write, last_read); record_allocation(ctx, allocator, reg_idx, writemask, first_write, last_read);
ret.id = reg_idx; ret.id = reg_idx;
ret.bind_count = 1; ret.allocation_size = 1;
ret.writemask = hlsl_combine_writemasks(writemask, (1u << component_count) - 1); ret.writemask = hlsl_combine_writemasks(writemask, (1u << component_count) - 1);
ret.allocated = true; ret.allocated = true;
return ret; return ret;
@ -3180,7 +3180,7 @@ static struct hlsl_reg allocate_range(struct hlsl_ctx *ctx, struct register_allo
record_allocation(ctx, allocator, reg_idx + i, VKD3DSP_WRITEMASK_ALL, first_write, last_read); record_allocation(ctx, allocator, reg_idx + i, VKD3DSP_WRITEMASK_ALL, first_write, last_read);
ret.id = reg_idx; ret.id = reg_idx;
ret.bind_count = align(reg_size, 4) / 4; ret.allocation_size = align(reg_size, 4) / 4;
ret.allocated = true; ret.allocated = true;
return ret; return ret;
} }
@ -3306,7 +3306,7 @@ static void calculate_resource_register_counts(struct hlsl_ctx *ctx)
/* Samplers (and textures separated from them) are only allocated until the last /* Samplers (and textures separated from them) are only allocated until the last
* used one. */ * used one. */
if (var->objects_usage[k][i].used) if (var->objects_usage[k][i].used)
var->regs[k].bind_count = (k == HLSL_REGSET_SAMPLERS || is_separated) ? i + 1 : type->reg_size[k]; var->regs[k].allocation_size = (k == HLSL_REGSET_SAMPLERS || is_separated) ? i + 1 : type->reg_size[k];
} }
} }
} }
@ -3613,7 +3613,7 @@ static void allocate_semantic_register(struct hlsl_ctx *ctx, struct hlsl_ir_var
{ {
var->regs[HLSL_REGSET_NUMERIC].allocated = true; var->regs[HLSL_REGSET_NUMERIC].allocated = true;
var->regs[HLSL_REGSET_NUMERIC].id = (*counter)++; var->regs[HLSL_REGSET_NUMERIC].id = (*counter)++;
var->regs[HLSL_REGSET_NUMERIC].bind_count = 1; var->regs[HLSL_REGSET_NUMERIC].allocation_size = 1;
var->regs[HLSL_REGSET_NUMERIC].writemask = (1 << var->data_type->dimx) - 1; var->regs[HLSL_REGSET_NUMERIC].writemask = (1 << var->data_type->dimx) - 1;
TRACE("Allocated %s to %s.\n", var->name, debug_register(output ? 'o' : 'v', TRACE("Allocated %s to %s.\n", var->name, debug_register(output ? 'o' : 'v',
var->regs[HLSL_REGSET_NUMERIC], var->data_type)); var->regs[HLSL_REGSET_NUMERIC], var->data_type));
@ -3792,7 +3792,7 @@ static void allocate_buffers(struct hlsl_ctx *ctx)
} }
buffer->reg.id = buffer->reservation.reg_index; buffer->reg.id = buffer->reservation.reg_index;
buffer->reg.bind_count = 1; buffer->reg.allocation_size = 1;
buffer->reg.allocated = true; buffer->reg.allocated = true;
TRACE("Allocated reserved %s to cb%u.\n", buffer->name, index); TRACE("Allocated reserved %s to cb%u.\n", buffer->name, index);
} }
@ -3802,7 +3802,7 @@ static void allocate_buffers(struct hlsl_ctx *ctx)
++index; ++index;
buffer->reg.id = index; buffer->reg.id = index;
buffer->reg.bind_count = 1; buffer->reg.allocation_size = 1;
buffer->reg.allocated = true; buffer->reg.allocated = true;
TRACE("Allocated %s to cb%u.\n", buffer->name, index); TRACE("Allocated %s to cb%u.\n", buffer->name, index);
++index; ++index;
@ -3842,7 +3842,7 @@ static const struct hlsl_ir_var *get_allocated_object(struct hlsl_ctx *ctx, enum
else if (var->regs[regset].allocated) else if (var->regs[regset].allocated)
{ {
start = var->regs[regset].id; start = var->regs[regset].id;
count = var->regs[regset].bind_count; count = var->regs[regset].allocation_size;
} }
else else
{ {
@ -3873,7 +3873,7 @@ static void allocate_objects(struct hlsl_ctx *ctx, enum hlsl_regset regset)
LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry) LIST_FOR_EACH_ENTRY(var, &ctx->extern_vars, struct hlsl_ir_var, extern_entry)
{ {
unsigned int count = var->regs[regset].bind_count; unsigned int count = var->regs[regset].allocation_size;
if (count == 0) if (count == 0)
continue; continue;

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@ -3119,7 +3119,7 @@ static struct extern_resource *sm4_get_extern_resources(struct hlsl_ctx *ctx, un
regset = hlsl_type_get_regset(component_type); regset = hlsl_type_get_regset(component_type);
regset_offset = hlsl_type_get_component_offset(ctx, var->data_type, regset, k); regset_offset = hlsl_type_get_component_offset(ctx, var->data_type, regset, k);
if (regset_offset > var->regs[regset].bind_count) if (regset_offset > var->regs[regset].allocation_size)
continue; continue;
if (var->objects_usage[regset][regset_offset].used) if (var->objects_usage[regset][regset_offset].used)
@ -3192,7 +3192,7 @@ static struct extern_resource *sm4_get_extern_resources(struct hlsl_ctx *ctx, un
extern_resources[*count].regset = regset; extern_resources[*count].regset = regset;
extern_resources[*count].id = var->regs[regset].id; extern_resources[*count].id = var->regs[regset].id;
extern_resources[*count].bind_count = var->regs[regset].bind_count; extern_resources[*count].bind_count = var->regs[regset].allocation_size;
++*count; ++*count;
} }