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vkd3d-shader/hlsl: Rename hlsl_ir_expr_op members.

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For the sake of simplicity and clarity, especially in the interest of allowing
us to have expressions with larger numbers of terms.

Signed-off-by: Zebediah Figura <zfigura@codeweavers.com>
Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com>
Signed-off-by: Matteo Bruni <mbruni@codeweavers.com>
Signed-off-by: Alexandre Julliard <julliard@winehq.org>
This commit is contained in:
Zebediah Figura
2021-08-12 19:36:13 -05:00
committed by Alexandre Julliard
parent b65789e74a
commit 7960f9e373
5 changed files with 134 additions and 146 deletions
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88
libs/vkd3d-shader/hlsl.c
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@@ -439,7 +439,7 @@ struct hlsl_ir_expr *hlsl_new_cast(struct hlsl_ctx *ctx, struct hlsl_ir_node *no
{
struct hlsl_ir_node *cast;
cast = hlsl_new_unary_expr(ctx, HLSL_IR_UNOP_CAST, node, *loc);
cast = hlsl_new_unary_expr(ctx, HLSL_OP1_CAST, node, *loc);
if (cast)
cast->data_type = type;
return hlsl_ir_expr(cast);
@@ -1035,51 +1035,51 @@ static const char *debug_expr_op(const struct hlsl_ir_expr *expr)
{
static const char *const op_names[] =
{
[HLSL_IR_UNOP_ABS] = "abs",
[HLSL_IR_UNOP_BIT_NOT] = "~",
[HLSL_IR_UNOP_CAST] = "cast",
[HLSL_IR_UNOP_COS] = "cos",
[HLSL_IR_UNOP_COS_REDUCED] = "cos_reduced",
[HLSL_IR_UNOP_DSX] = "dsx",
[HLSL_IR_UNOP_DSY] = "dsy",
[HLSL_IR_UNOP_EXP2] = "exp2",
[HLSL_IR_UNOP_FRACT] = "fract",
[HLSL_IR_UNOP_LOG2] = "log2",
[HLSL_IR_UNOP_LOGIC_NOT] = "!",
[HLSL_IR_UNOP_NEG] = "-",
[HLSL_IR_UNOP_NRM] = "nrm",
[HLSL_IR_UNOP_RCP] = "rcp",
[HLSL_IR_UNOP_RSQ] = "rsq",
[HLSL_IR_UNOP_SAT] = "sat",
[HLSL_IR_UNOP_SIGN] = "sign",
[HLSL_IR_UNOP_SIN] = "sin",
[HLSL_IR_UNOP_SIN_REDUCED] = "sin_reduced",
[HLSL_IR_UNOP_SQRT] = "sqrt",
[HLSL_OP1_ABS] = "abs",
[HLSL_OP1_BIT_NOT] = "~",
[HLSL_OP1_CAST] = "cast",
[HLSL_OP1_COS] = "cos",
[HLSL_OP1_COS_REDUCED] = "cos_reduced",
[HLSL_OP1_DSX] = "dsx",
[HLSL_OP1_DSY] = "dsy",
[HLSL_OP1_EXP2] = "exp2",
[HLSL_OP1_FRACT] = "fract",
[HLSL_OP1_LOG2] = "log2",
[HLSL_OP1_LOGIC_NOT] = "!",
[HLSL_OP1_NEG] = "-",
[HLSL_OP1_NRM] = "nrm",
[HLSL_OP1_RCP] = "rcp",
[HLSL_OP1_RSQ] = "rsq",
[HLSL_OP1_SAT] = "sat",
[HLSL_OP1_SIGN] = "sign",
[HLSL_OP1_SIN] = "sin",
[HLSL_OP1_SIN_REDUCED] = "sin_reduced",
[HLSL_OP1_SQRT] = "sqrt",
[HLSL_IR_BINOP_ADD] = "+",
[HLSL_IR_BINOP_BIT_AND] = "&",
[HLSL_IR_BINOP_BIT_OR] = "|",
[HLSL_IR_BINOP_BIT_XOR] = "^",
[HLSL_IR_BINOP_CRS] = "crs",
[HLSL_IR_BINOP_DIV] = "/",
[HLSL_IR_BINOP_DOT] = "dot",
[HLSL_IR_BINOP_EQUAL] = "==",
[HLSL_IR_BINOP_GEQUAL] = ">=",
[HLSL_IR_BINOP_GREATER] = ">",
[HLSL_IR_BINOP_LEQUAL] = "<=",
[HLSL_IR_BINOP_LESS] = "<",
[HLSL_IR_BINOP_LOGIC_AND] = "&&",
[HLSL_IR_BINOP_LOGIC_OR] = "||",
[HLSL_IR_BINOP_LSHIFT] = "<<",
[HLSL_IR_BINOP_MAX] = "max",
[HLSL_IR_BINOP_MIN] = "min",
[HLSL_IR_BINOP_MOD] = "%",
[HLSL_IR_BINOP_MUL] = "*",
[HLSL_IR_BINOP_NEQUAL] = "!=",
[HLSL_IR_BINOP_POW] = "pow",
[HLSL_IR_BINOP_RSHIFT] = ">>",
[HLSL_OP2_ADD] = "+",
[HLSL_OP2_BIT_AND] = "&",
[HLSL_OP2_BIT_OR] = "|",
[HLSL_OP2_BIT_XOR] = "^",
[HLSL_OP2_CRS] = "crs",
[HLSL_OP2_DIV] = "/",
[HLSL_OP2_DOT] = "dot",
[HLSL_OP2_EQUAL] = "==",
[HLSL_OP2_GEQUAL] = ">=",
[HLSL_OP2_GREATER] = ">",
[HLSL_OP2_LEQUAL] = "<=",
[HLSL_OP2_LESS] = "<",
[HLSL_OP2_LOGIC_AND] = "&&",
[HLSL_OP2_LOGIC_OR] = "||",
[HLSL_OP2_LSHIFT] = "<<",
[HLSL_OP2_MAX] = "max",
[HLSL_OP2_MIN] = "min",
[HLSL_OP2_MOD] = "%",
[HLSL_OP2_MUL] = "*",
[HLSL_OP2_NEQUAL] = "!=",
[HLSL_OP2_POW] = "pow",
[HLSL_OP2_RSHIFT] = ">>",
[HLSL_IR_TEROP_LERP] = "lerp",
[HLSL_OP3_LERP] = "lerp",
};
return op_names[expr->op];