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vkd3d-shader/hlsl: Save DP2ADD hlsl_ir_exprs in the vsir_program for SM1.
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parent
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commit
6e6e2910d6
Notes:
Henri Verbeet
2024-09-11 15:33:53 +02:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1041
@ -1960,33 +1960,6 @@ static void sm1_map_src_swizzle(struct sm1_src_register *src, unsigned int map_w
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src->swizzle = hlsl_map_swizzle(src->swizzle, map_writemask);
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src->swizzle = hlsl_map_swizzle(src->swizzle, map_writemask);
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}
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}
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static void d3dbc_write_dp2add(struct d3dbc_compiler *d3dbc, const struct hlsl_reg *dst,
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const struct hlsl_reg *src1, const struct hlsl_reg *src2, const struct hlsl_reg *src3)
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{
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struct sm1_instruction instr =
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{
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.opcode = VKD3D_SM1_OP_DP2ADD,
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.dst.type = VKD3DSPR_TEMP,
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.dst.writemask = dst->writemask,
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.dst.reg = dst->id,
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.has_dst = 1,
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.srcs[0].type = VKD3DSPR_TEMP,
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.srcs[0].swizzle = hlsl_swizzle_from_writemask(src1->writemask),
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.srcs[0].reg = src1->id,
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.srcs[1].type = VKD3DSPR_TEMP,
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.srcs[1].swizzle = hlsl_swizzle_from_writemask(src2->writemask),
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.srcs[1].reg = src2->id,
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.srcs[2].type = VKD3DSPR_TEMP,
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.srcs[2].swizzle = hlsl_swizzle_from_writemask(src3->writemask),
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.srcs[2].reg = src3->id,
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.src_count = 3,
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};
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d3dbc_write_instruction(d3dbc, &instr);
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}
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static void d3dbc_write_unary_op(struct d3dbc_compiler *d3dbc, enum vkd3d_sm1_opcode opcode,
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static void d3dbc_write_unary_op(struct d3dbc_compiler *d3dbc, enum vkd3d_sm1_opcode opcode,
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const struct hlsl_reg *dst, const struct hlsl_reg *src,
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const struct hlsl_reg *dst, const struct hlsl_reg *src,
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D3DSHADER_PARAM_SRCMOD_TYPE src_mod, D3DSHADER_PARAM_DSTMOD_TYPE dst_mod)
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D3DSHADER_PARAM_SRCMOD_TYPE src_mod, D3DSHADER_PARAM_DSTMOD_TYPE dst_mod)
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@ -2316,6 +2289,7 @@ static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const str
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case VKD3DSIH_ABS:
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case VKD3DSIH_ABS:
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case VKD3DSIH_ADD:
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case VKD3DSIH_ADD:
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case VKD3DSIH_CMP:
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case VKD3DSIH_CMP:
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case VKD3DSIH_DP2ADD:
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case VKD3DSIH_DP3:
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case VKD3DSIH_DP3:
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case VKD3DSIH_DP4:
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case VKD3DSIH_DP4:
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case VKD3DSIH_DSX:
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case VKD3DSIH_DSX:
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@ -2425,8 +2399,6 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
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{
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{
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struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
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struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
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struct hlsl_ir_node *arg1 = expr->operands[0].node;
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struct hlsl_ir_node *arg1 = expr->operands[0].node;
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struct hlsl_ir_node *arg2 = expr->operands[1].node;
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struct hlsl_ir_node *arg3 = expr->operands[2].node;
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struct hlsl_ctx *ctx = d3dbc->ctx;
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struct hlsl_ctx *ctx = d3dbc->ctx;
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VKD3D_ASSERT(instr->reg.allocated);
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VKD3D_ASSERT(instr->reg.allocated);
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@ -2450,16 +2422,7 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
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return;
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return;
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}
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}
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switch (expr->op)
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hlsl_fixme(ctx, &instr->loc, "SM1 \"%s\" expression.", debug_hlsl_expr_op(expr->op));
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{
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case HLSL_OP3_DP2ADD:
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d3dbc_write_dp2add(d3dbc, &instr->reg, &arg1->reg, &arg2->reg, &arg3->reg);
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break;
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default:
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hlsl_fixme(ctx, &instr->loc, "SM1 \"%s\" expression.", debug_hlsl_expr_op(expr->op));
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break;
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}
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}
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}
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static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_block *block);
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static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_block *block);
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@ -715,7 +715,7 @@ enum hlsl_ir_expr_op
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HLSL_OP2_SLT,
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HLSL_OP2_SLT,
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/* DP2ADD(a, b, c) computes the scalar product of a.xy and b.xy,
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/* DP2ADD(a, b, c) computes the scalar product of a.xy and b.xy,
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* then adds c. */
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* then adds c, where c must have dimx=1. */
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HLSL_OP3_DP2ADD,
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HLSL_OP3_DP2ADD,
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/* TERNARY(a, b, c) returns 'b' if 'a' is true and 'c' otherwise. 'a' must always be boolean.
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/* TERNARY(a, b, c) returns 'b' if 'a' is true and 'c' otherwise. 'a' must always be boolean.
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* CMP(a, b, c) returns 'b' if 'a' >= 0, and 'c' otherwise. It's used only for SM1-SM3 targets. */
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* CMP(a, b, c) returns 'b' if 'a' >= 0, and 'c' otherwise. It's used only for SM1-SM3 targets. */
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@ -6788,6 +6788,10 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_CMP, 0, 0, true);
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_CMP, 0, 0, true);
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break;
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break;
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case HLSL_OP3_DP2ADD:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DP2ADD, 0, 0, false);
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break;
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case HLSL_OP3_MAD:
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case HLSL_OP3_MAD:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAD, 0, 0, true);
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAD, 0, 0, true);
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break;
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break;
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