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vkd3d-shader/hlsl: Store SM4 ABS instructions in the vsir program.
This commit is contained in:
Francisco Casas
Henri Verbeet
parent
404644bad3
commit
68311ef010
Notes:
Henri Verbeet
2024-11-04 17:12:25 +01:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1242
@ -6843,9 +6843,9 @@ static void sm1_generate_vsir_instr_constant(struct hlsl_ctx *ctx,
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}
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/* Translate ops that can be mapped to a single vsir instruction with only one dst register. */
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static void sm1_generate_vsir_instr_expr_single_instr_op(struct hlsl_ctx *ctx, struct vsir_program *program,
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struct hlsl_ir_expr *expr, enum vkd3d_shader_opcode opcode, uint32_t src_mod, uint32_t dst_mod,
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bool map_src_swizzles)
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static void generate_vsir_instr_expr_single_instr_op(struct hlsl_ctx *ctx,
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struct vsir_program *program, struct hlsl_ir_expr *expr, enum vkd3d_shader_opcode opcode,
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uint32_t src_mod, uint32_t dst_mod, bool map_src_swizzles)
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{
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struct hlsl_ir_node *instr = &expr->node;
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struct vkd3d_shader_dst_param *dst_param;
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@ -6866,8 +6866,9 @@ static void sm1_generate_vsir_instr_expr_single_instr_op(struct hlsl_ctx *ctx, s
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return;
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dst_param = &ins->dst[0];
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vsir_register_init(&dst_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
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vsir_register_init(&dst_param->reg, VKD3DSPR_TEMP, vsir_data_type_from_hlsl_instruction(ctx, instr), 1);
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dst_param->reg.idx[0].offset = instr->reg.id;
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dst_param->reg.dimension = VSIR_DIMENSION_VEC4;
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dst_param->write_mask = instr->reg.writemask;
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dst_param->modifiers = dst_mod;
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@ -6986,13 +6987,13 @@ static bool sm1_generate_vsir_instr_expr_cast(struct hlsl_ctx *ctx,
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/* Integrals are internally represented as floats, so no change is necessary.*/
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case HLSL_TYPE_HALF:
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case HLSL_TYPE_FLOAT:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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return true;
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case HLSL_TYPE_DOUBLE:
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if (ctx->double_as_float_alias)
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{
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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return true;
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}
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hlsl_error(ctx, &instr->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TYPE,
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@ -7017,7 +7018,7 @@ static bool sm1_generate_vsir_instr_expr_cast(struct hlsl_ctx *ctx,
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case HLSL_TYPE_INT:
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case HLSL_TYPE_UINT:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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return true;
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case HLSL_TYPE_BOOL:
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@ -7039,7 +7040,7 @@ static bool sm1_generate_vsir_instr_expr_cast(struct hlsl_ctx *ctx,
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case HLSL_TYPE_FLOAT:
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if (ctx->double_as_float_alias)
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{
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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return true;
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}
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hlsl_error(ctx, &instr->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TYPE,
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@ -7079,7 +7080,7 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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switch (expr->op)
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{
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case HLSL_OP1_ABS:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ABS, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ABS, 0, 0, true);
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break;
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case HLSL_OP1_CAST:
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@ -7091,11 +7092,11 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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break;
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case HLSL_OP1_DSX:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DSX, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DSX, 0, 0, true);
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break;
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case HLSL_OP1_DSY:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DSY, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DSY, 0, 0, true);
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break;
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case HLSL_OP1_EXP2:
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@ -7107,7 +7108,7 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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break;
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case HLSL_OP1_NEG:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, VKD3DSPSM_NEG, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, VKD3DSPSM_NEG, 0, true);
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break;
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case HLSL_OP1_RCP:
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@ -7115,7 +7116,7 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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break;
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case HLSL_OP1_REINTERPRET:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, 0, true);
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break;
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case HLSL_OP1_RSQ:
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@ -7123,7 +7124,7 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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break;
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case HLSL_OP1_SAT:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, VKD3DSPDM_SATURATE, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, VKD3DSPDM_SATURATE, true);
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break;
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case HLSL_OP1_SIN_REDUCED:
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@ -7132,18 +7133,18 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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break;
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case HLSL_OP2_ADD:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ADD, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ADD, 0, 0, true);
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break;
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case HLSL_OP2_DOT:
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switch (expr->operands[0].node->data_type->dimx)
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{
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case 3:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DP3, 0, 0, false);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DP3, 0, 0, false);
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break;
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case 4:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DP4, 0, 0, false);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DP4, 0, 0, false);
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break;
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default:
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@ -7153,43 +7154,43 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
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break;
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case HLSL_OP2_MAX:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAX, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAX, 0, 0, true);
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break;
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case HLSL_OP2_MIN:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MIN, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MIN, 0, 0, true);
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break;
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case HLSL_OP2_MUL:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MUL, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MUL, 0, 0, true);
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break;
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case HLSL_OP1_FRACT:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_FRC, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_FRC, 0, 0, true);
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break;
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case HLSL_OP2_LOGIC_AND:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MIN, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MIN, 0, 0, true);
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break;
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case HLSL_OP2_LOGIC_OR:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAX, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAX, 0, 0, true);
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break;
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case HLSL_OP2_SLT:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_SLT, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_SLT, 0, 0, true);
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break;
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case HLSL_OP3_CMP:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_CMP, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_CMP, 0, 0, true);
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break;
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case HLSL_OP3_DP2ADD:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DP2ADD, 0, 0, false);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DP2ADD, 0, 0, false);
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break;
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case HLSL_OP3_MAD:
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sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAD, 0, 0, true);
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MAD, 0, 0, true);
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break;
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default:
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@ -7673,6 +7674,20 @@ static void sm4_generate_vsir_instr_dcl_indexable_temp(struct hlsl_ctx *ctx,
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add_last_vsir_instr_to_block(ctx, program, block);
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}
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static bool sm4_generate_vsir_instr_expr(struct hlsl_ctx *ctx,
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struct vsir_program *program, struct hlsl_ir_expr *expr)
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{
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switch (expr->op)
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{
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case HLSL_OP1_ABS:
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generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, VKD3DSPSM_ABS, 0, true);
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return true;
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default:
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return false;
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}
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}
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static void sm4_generate_vsir_block(struct hlsl_ctx *ctx, struct hlsl_block *block, struct vsir_program *program)
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{
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struct hlsl_ir_node *instr, *next;
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@ -7697,6 +7712,11 @@ static void sm4_generate_vsir_block(struct hlsl_ctx *ctx, struct hlsl_block *blo
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/* In SM4 all constants are inlined. */
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break;
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case HLSL_IR_EXPR:
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if (sm4_generate_vsir_instr_expr(ctx, program, hlsl_ir_expr(instr)))
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replace_instr_with_last_vsir_instr(ctx, program, instr);
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break;
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case HLSL_IR_SWIZZLE:
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generate_vsir_instr_swizzle(ctx, program, hlsl_ir_swizzle(instr));
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replace_instr_with_last_vsir_instr(ctx, program, instr);
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