From 65f3f56f63948cb51dd460401792b2d7b194def9 Mon Sep 17 00:00:00 2001 From: Elizabeth Figura Date: Sat, 20 Jul 2024 12:26:56 -0500 Subject: [PATCH] vkd3d-shader/d3dbc: Normalize to a single VKD3DSPR_CONST register set when reading. We don't need VKD3DSPR_CONST2 et al in the IR, even for disassembly. --- libs/vkd3d-shader/d3d_asm.c | 23 +------ libs/vkd3d-shader/d3dbc.c | 81 +++++++++++++++--------- libs/vkd3d-shader/ir.c | 12 ++-- libs/vkd3d-shader/vkd3d_shader_private.h | 3 - 4 files changed, 56 insertions(+), 63 deletions(-) diff --git a/libs/vkd3d-shader/d3d_asm.c b/libs/vkd3d-shader/d3d_asm.c index 8c96befa..ff14e023 100644 --- a/libs/vkd3d-shader/d3d_asm.c +++ b/libs/vkd3d-shader/d3d_asm.c @@ -377,22 +377,6 @@ struct vkd3d_d3d_asm_compiler const struct vkd3d_shader_instruction *current; }; -/* Convert floating point offset relative to a register file to an absolute - * offset for float constants. */ -static unsigned int shader_get_float_offset(enum vkd3d_shader_register_type register_type, UINT register_idx) -{ - switch (register_type) - { - case VKD3DSPR_CONST: return register_idx; - case VKD3DSPR_CONST2: return 2048 + register_idx; - case VKD3DSPR_CONST3: return 4096 + register_idx; - case VKD3DSPR_CONST4: return 6144 + register_idx; - default: - FIXME("Unsupported register type: %u.\n", register_type); - return register_idx; - } -} - static void shader_dump_global_flags(struct vkd3d_d3d_asm_compiler *compiler, enum vsir_global_flags global_flags) { unsigned int i; @@ -975,11 +959,7 @@ static void shader_print_register(struct vkd3d_d3d_asm_compiler *compiler, const break; case VKD3DSPR_CONST: - case VKD3DSPR_CONST2: - case VKD3DSPR_CONST3: - case VKD3DSPR_CONST4: vkd3d_string_buffer_printf(buffer, "c"); - offset = shader_get_float_offset(reg->type, offset); break; case VKD3DSPR_TEXTURE: /* vs: case VKD3DSPR_ADDR */ @@ -2132,8 +2112,7 @@ static void shader_dump_instruction(struct vkd3d_d3d_asm_compiler *compiler, case VKD3DSIH_DEF: vkd3d_string_buffer_printf(buffer, " %sc%u%s", compiler->colours.reg, - shader_get_float_offset(ins->dst[0].reg.type, ins->dst[0].reg.idx[0].offset), - compiler->colours.reset); + ins->dst[0].reg.idx[0].offset, compiler->colours.reset); shader_print_float_literal(compiler, " = ", ins->src[0].reg.u.immconst_f32[0], ""); shader_print_float_literal(compiler, ", ", ins->src[0].reg.u.immconst_f32[1], ""); shader_print_float_literal(compiler, ", ", ins->src[0].reg.u.immconst_f32[2], ""); diff --git a/libs/vkd3d-shader/d3dbc.c b/libs/vkd3d-shader/d3dbc.c index 324fccc8..17f96dbc 100644 --- a/libs/vkd3d-shader/d3dbc.c +++ b/libs/vkd3d-shader/d3dbc.c @@ -432,9 +432,6 @@ register_types[] = {VKD3D_SM1_REG_COLOROUT, VKD3DSPR_COLOROUT}, {VKD3D_SM1_REG_DEPTHOUT, VKD3DSPR_DEPTHOUT}, {VKD3D_SM1_REG_SAMPLER, VKD3DSPR_COMBINED_SAMPLER}, - {VKD3D_SM1_REG_CONST2, VKD3DSPR_CONST2}, - {VKD3D_SM1_REG_CONST3, VKD3DSPR_CONST3}, - {VKD3D_SM1_REG_CONST4, VKD3DSPR_CONST4}, {VKD3D_SM1_REG_CONSTBOOL, VKD3DSPR_CONSTBOOL}, {VKD3D_SM1_REG_LOOP, VKD3DSPR_LOOP}, {VKD3D_SM1_REG_TEMPFLOAT16, VKD3DSPR_TEMPFLOAT16}, @@ -515,11 +512,31 @@ static unsigned int idx_count_from_reg_type(enum vkd3d_shader_register_type reg_ } } -static enum vkd3d_shader_register_type parse_register_type(uint32_t param) +static enum vkd3d_shader_register_type parse_register_type(uint32_t param, unsigned int *index_offset) { enum vkd3d_sm1_register_type d3dbc_type = ((param & VKD3D_SM1_REGISTER_TYPE_MASK) >> VKD3D_SM1_REGISTER_TYPE_SHIFT) | ((param & VKD3D_SM1_REGISTER_TYPE_MASK2) >> VKD3D_SM1_REGISTER_TYPE_SHIFT2); + *index_offset = 0; + + if (d3dbc_type == VKD3D_SM1_REG_CONST2) + { + *index_offset = 2048; + return VKD3DSPR_CONST; + } + + if (d3dbc_type == VKD3D_SM1_REG_CONST3) + { + *index_offset = 4096; + return VKD3DSPR_CONST; + } + + if (d3dbc_type == VKD3D_SM1_REG_CONST4) + { + *index_offset = 6144; + return VKD3DSPR_CONST; + } + for (unsigned int i = 0; i < ARRAY_SIZE(register_types); ++i) { if (register_types[i].d3dbc_type == d3dbc_type) @@ -532,15 +549,17 @@ static enum vkd3d_shader_register_type parse_register_type(uint32_t param) static void shader_sm1_parse_src_param(uint32_t param, struct vkd3d_shader_src_param *rel_addr, struct vkd3d_shader_src_param *src) { - enum vkd3d_shader_register_type reg_type = parse_register_type(param); - unsigned int idx_count = idx_count_from_reg_type(reg_type); + enum vkd3d_shader_register_type reg_type; + unsigned int index_offset, idx_count; + reg_type = parse_register_type(param, &index_offset); + idx_count = idx_count_from_reg_type(reg_type); vsir_register_init(&src->reg, reg_type, VKD3D_DATA_FLOAT, idx_count); src->reg.precision = VKD3D_SHADER_REGISTER_PRECISION_DEFAULT; src->reg.non_uniform = false; if (idx_count == 1) { - src->reg.idx[0].offset = param & VKD3D_SM1_REGISTER_NUMBER_MASK; + src->reg.idx[0].offset = index_offset + (param & VKD3D_SM1_REGISTER_NUMBER_MASK); src->reg.idx[0].rel_addr = rel_addr; } if (src->reg.type == VKD3DSPR_SAMPLER) @@ -556,15 +575,17 @@ static void shader_sm1_parse_src_param(uint32_t param, struct vkd3d_shader_src_p static void shader_sm1_parse_dst_param(uint32_t param, struct vkd3d_shader_src_param *rel_addr, struct vkd3d_shader_dst_param *dst) { - enum vkd3d_shader_register_type reg_type = parse_register_type(param); - unsigned int idx_count = idx_count_from_reg_type(reg_type); + enum vkd3d_shader_register_type reg_type; + unsigned int index_offset, idx_count; + reg_type = parse_register_type(param, &index_offset); + idx_count = idx_count_from_reg_type(reg_type); vsir_register_init(&dst->reg, reg_type, VKD3D_DATA_FLOAT, idx_count); dst->reg.precision = VKD3D_SHADER_REGISTER_PRECISION_DEFAULT; dst->reg.non_uniform = false; if (idx_count == 1) { - dst->reg.idx[0].offset = param & VKD3D_SM1_REGISTER_NUMBER_MASK; + dst->reg.idx[0].offset = index_offset + (param & VKD3D_SM1_REGISTER_NUMBER_MASK); dst->reg.idx[0].rel_addr = rel_addr; } if (dst->reg.type == VKD3DSPR_SAMPLER) @@ -909,18 +930,6 @@ static void shader_sm1_scan_register(struct vkd3d_shader_sm1_parser *sm1, record_constant_register(sm1, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, register_index, from_def); break; - case VKD3DSPR_CONST2: - record_constant_register(sm1, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 2048 + register_index, from_def); - break; - - case VKD3DSPR_CONST3: - record_constant_register(sm1, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 4096 + register_index, from_def); - break; - - case VKD3DSPR_CONST4: - record_constant_register(sm1, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 6144 + register_index, from_def); - break; - case VKD3DSPR_CONSTINT: record_constant_register(sm1, VKD3D_SHADER_D3DBC_INT_CONSTANT_REGISTER, register_index, from_def); break; @@ -1688,20 +1697,30 @@ static void d3dbc_write_comment(struct d3dbc_compiler *d3dbc, set_u32(buffer, offset, vkd3d_make_u32(VKD3D_SM1_OP_COMMENT, (end - start) / sizeof(uint32_t))); } -static enum vkd3d_sm1_register_type d3dbc_register_type_from_vsir(enum vkd3d_shader_register_type type) +static enum vkd3d_sm1_register_type d3dbc_register_type_from_vsir(const struct vkd3d_shader_register *reg) { + if (reg->type == VKD3DSPR_CONST) + { + if (reg->idx[0].offset >= 6144) + return VKD3D_SM1_REG_CONST4; + if (reg->idx[0].offset >= 4096) + return VKD3D_SM1_REG_CONST3; + if (reg->idx[0].offset >= 2048) + return VKD3D_SM1_REG_CONST2; + } + for (unsigned int i = 0; i < ARRAY_SIZE(register_types); ++i) { - if (register_types[i].vsir_type == type) + if (register_types[i].vsir_type == reg->type) return register_types[i].d3dbc_type; } vkd3d_unreachable(); } -static uint32_t sm1_encode_register_type(enum vkd3d_shader_register_type type) +static uint32_t sm1_encode_register_type(const struct vkd3d_shader_register *reg) { - enum vkd3d_sm1_register_type sm1_type = d3dbc_register_type_from_vsir(type); + enum vkd3d_sm1_register_type sm1_type = d3dbc_register_type_from_vsir(reg); return ((sm1_type << VKD3D_SM1_REGISTER_TYPE_SHIFT) & VKD3D_SM1_REGISTER_TYPE_MASK) | ((sm1_type << VKD3D_SM1_REGISTER_TYPE_SHIFT2) & VKD3D_SM1_REGISTER_TYPE_MASK2); @@ -1753,17 +1772,19 @@ static void write_sm1_dst_register(struct vkd3d_bytecode_buffer *buffer, const s { VKD3D_ASSERT(reg->write_mask); put_u32(buffer, VKD3D_SM1_INSTRUCTION_PARAMETER - | sm1_encode_register_type(reg->reg.type) + | sm1_encode_register_type(®->reg) | (reg->modifiers << VKD3D_SM1_DST_MODIFIER_SHIFT) - | (reg->write_mask << VKD3D_SM1_WRITEMASK_SHIFT) | reg->reg.idx[0].offset); + | (reg->write_mask << VKD3D_SM1_WRITEMASK_SHIFT) + | (reg->reg.idx[0].offset & VKD3D_SM1_REGISTER_NUMBER_MASK)); } static void write_sm1_src_register(struct vkd3d_bytecode_buffer *buffer, const struct vkd3d_shader_src_param *reg) { put_u32(buffer, VKD3D_SM1_INSTRUCTION_PARAMETER - | sm1_encode_register_type(reg->reg.type) + | sm1_encode_register_type(®->reg) | (reg->modifiers << VKD3D_SM1_SRC_MODIFIER_SHIFT) - | (swizzle_from_vsir(reg->swizzle) << VKD3D_SM1_SWIZZLE_SHIFT) | reg->reg.idx[0].offset); + | (swizzle_from_vsir(reg->swizzle) << VKD3D_SM1_SWIZZLE_SHIFT) + | (reg->reg.idx[0].offset & VKD3D_SM1_REGISTER_NUMBER_MASK)); } static void d3dbc_write_instruction(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_instruction *ins) diff --git a/libs/vkd3d-shader/ir.c b/libs/vkd3d-shader/ir.c index 1f12feb1..b45416da 100644 --- a/libs/vkd3d-shader/ir.c +++ b/libs/vkd3d-shader/ir.c @@ -2413,16 +2413,12 @@ static bool get_flat_constant_register_type(const struct vkd3d_shader_register * { enum vkd3d_shader_register_type type; enum vkd3d_shader_d3dbc_constant_register set; - uint32_t offset; } regs[] = { - {VKD3DSPR_CONST, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 0}, - {VKD3DSPR_CONST2, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 2048}, - {VKD3DSPR_CONST3, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 4096}, - {VKD3DSPR_CONST4, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 6144}, - {VKD3DSPR_CONSTINT, VKD3D_SHADER_D3DBC_INT_CONSTANT_REGISTER, 0}, - {VKD3DSPR_CONSTBOOL, VKD3D_SHADER_D3DBC_BOOL_CONSTANT_REGISTER, 0}, + {VKD3DSPR_CONST, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER}, + {VKD3DSPR_CONSTINT, VKD3D_SHADER_D3DBC_INT_CONSTANT_REGISTER}, + {VKD3DSPR_CONSTBOOL, VKD3D_SHADER_D3DBC_BOOL_CONSTANT_REGISTER}, }; unsigned int i; @@ -2438,7 +2434,7 @@ static bool get_flat_constant_register_type(const struct vkd3d_shader_register * } *set = regs[i].set; - *index = regs[i].offset + reg->idx[0].offset; + *index = reg->idx[0].offset; return true; } } diff --git a/libs/vkd3d-shader/vkd3d_shader_private.h b/libs/vkd3d-shader/vkd3d_shader_private.h index 08b45974..8ec9f11c 100644 --- a/libs/vkd3d-shader/vkd3d_shader_private.h +++ b/libs/vkd3d-shader/vkd3d_shader_private.h @@ -608,9 +608,6 @@ enum vkd3d_shader_register_type VKD3DSPR_COLOROUT, VKD3DSPR_DEPTHOUT, VKD3DSPR_COMBINED_SAMPLER, - VKD3DSPR_CONST2, - VKD3DSPR_CONST3, - VKD3DSPR_CONST4, VKD3DSPR_CONSTBOOL, VKD3DSPR_LOOP, VKD3DSPR_TEMPFLOAT16,