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https://gitlab.winehq.org/wine/vkd3d.git
synced 2024-11-21 16:46:41 -08:00
vkd3d-shader/hlsl: Write SM4 thread ID registers.
This commit is contained in:
parent
809a43f06b
commit
653cc02f4c
@ -49,21 +49,25 @@ bool hlsl_sm4_register_from_semantic(struct hlsl_ctx *ctx, const struct hlsl_sem
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const char *semantic;
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bool output;
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enum vkd3d_shader_type shader_type;
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enum vkd3d_sm4_register_type type;
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enum vkd3d_sm4_swizzle_type swizzle_type;
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enum vkd3d_sm4_register_type type;
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bool has_idx;
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}
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register_table[] =
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{
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{"sv_primitiveid", false, VKD3D_SHADER_TYPE_GEOMETRY, VKD3D_SM4_RT_PRIMID, VKD3D_SM4_SWIZZLE_NONE, false},
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{"sv_dispatchthreadid", false, VKD3D_SHADER_TYPE_COMPUTE, VKD3D_SM4_SWIZZLE_VEC4, VKD3D_SM5_RT_THREAD_ID, false},
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{"sv_groupid", false, VKD3D_SHADER_TYPE_COMPUTE, VKD3D_SM4_SWIZZLE_VEC4, VKD3D_SM5_RT_THREAD_GROUP_ID, false},
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{"sv_groupthreadid", false, VKD3D_SHADER_TYPE_COMPUTE, VKD3D_SM4_SWIZZLE_VEC4, VKD3D_SM5_RT_LOCAL_THREAD_ID, false},
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{"sv_primitiveid", false, VKD3D_SHADER_TYPE_GEOMETRY, VKD3D_SM4_SWIZZLE_NONE, VKD3D_SM4_RT_PRIMID, false},
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/* Put sv_target in this table, instead of letting it fall through to
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* default varying allocation, so that the register index matches the
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* usage index. */
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{"color", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_RT_OUTPUT, VKD3D_SM4_SWIZZLE_VEC4, true},
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{"depth", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_RT_DEPTHOUT, VKD3D_SM4_SWIZZLE_VEC4, false},
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{"sv_depth", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_RT_DEPTHOUT, VKD3D_SM4_SWIZZLE_VEC4, false},
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{"sv_target", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_RT_OUTPUT, VKD3D_SM4_SWIZZLE_VEC4, true},
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{"color", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_SWIZZLE_VEC4, VKD3D_SM4_RT_OUTPUT, true},
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{"depth", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_SWIZZLE_VEC4, VKD3D_SM4_RT_DEPTHOUT, false},
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{"sv_depth", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_SWIZZLE_VEC4, VKD3D_SM4_RT_DEPTHOUT, false},
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{"sv_target", true, VKD3D_SHADER_TYPE_PIXEL, VKD3D_SM4_SWIZZLE_VEC4, VKD3D_SM4_RT_OUTPUT, true},
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};
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for (i = 0; i < ARRAY_SIZE(register_table); ++i)
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@ -97,6 +101,10 @@ bool hlsl_sm4_usage_from_semantic(struct hlsl_ctx *ctx, const struct hlsl_semant
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}
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semantics[] =
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{
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{"sv_dispatchthreadid", false, VKD3D_SHADER_TYPE_COMPUTE, ~0u},
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{"sv_groupid", false, VKD3D_SHADER_TYPE_COMPUTE, ~0u},
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{"sv_groupthreadid", false, VKD3D_SHADER_TYPE_COMPUTE, ~0u},
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{"position", false, VKD3D_SHADER_TYPE_GEOMETRY, D3D_NAME_POSITION},
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{"sv_position", false, VKD3D_SHADER_TYPE_GEOMETRY, D3D_NAME_POSITION},
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{"sv_primitiveid", false, VKD3D_SHADER_TYPE_GEOMETRY, D3D_NAME_PRIMITIVE_ID},
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@ -164,6 +172,8 @@ static void write_sm4_signature(struct hlsl_ctx *ctx, struct dxbc_writer *dxbc,
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ret = hlsl_sm4_usage_from_semantic(ctx, &var->semantic, output, &usage);
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assert(ret);
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if (usage == ~0u)
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continue;
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usage_idx = var->semantic.index;
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if (hlsl_sm4_register_from_semantic(ctx, &var->semantic, output, &type, NULL, &has_idx))
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@ -226,6 +236,8 @@ static void write_sm4_signature(struct hlsl_ctx *ctx, struct dxbc_writer *dxbc,
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continue;
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hlsl_sm4_usage_from_semantic(ctx, &var->semantic, output, &usage);
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if (usage == ~0u)
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continue;
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if (usage == D3D_NAME_TARGET && !ascii_strcasecmp(semantic, "color"))
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string_offset = put_string(&buffer, "SV_Target");
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@ -1205,6 +1217,8 @@ static void write_sm4_dcl_semantic(struct hlsl_ctx *ctx, struct vkd3d_bytecode_b
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instr.dsts[0].reg.dim = VKD3D_SM4_DIMENSION_SCALAR;
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hlsl_sm4_usage_from_semantic(ctx, &var->semantic, output, &usage);
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if (usage == ~0u)
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usage = D3D_NAME_UNDEFINED;
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if (var->is_input_semantic)
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{
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@ -171,7 +171,7 @@ size (2, 2)
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1.0 1.0
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1.0 1.0
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[compute shader todo]
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[compute shader]
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/* Attributes are taken from the first function, and dropped from the second. */
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RWTexture2D<float> u;
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@ -185,7 +185,7 @@ void main(uint2 id : sv_dispatchthreadid)
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}
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[test]
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todo dispatch 1 1 1
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dispatch 1 1 1
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probe uav 0 (0, 0) r (2.0)
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probe uav 0 (0, 1) r (1.0)
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probe uav 0 (1, 0) r (2.0)
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@ -488,87 +488,84 @@ static void test_thread_id(void)
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get_cpu_descriptor_handle(&context, heap, i));
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}
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todo cs_code = compile_shader(cs_source, "cs_5_0");
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if (cs_code)
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cs_code = compile_shader(cs_source, "cs_5_0");
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context.pipeline_state = create_compute_pipeline_state(device, context.root_signature,
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shader_bytecode(ID3D10Blob_GetBufferPointer(cs_code), ID3D10Blob_GetBufferSize(cs_code)));
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ID3D12GraphicsCommandList_SetPipelineState(command_list, context.pipeline_state);
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ID3D12GraphicsCommandList_SetComputeRootSignature(command_list, context.root_signature);
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ID3D12GraphicsCommandList_SetComputeRootDescriptorTable(command_list,
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0, get_gpu_descriptor_handle(&context, heap, 0));
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ID3D12GraphicsCommandList_Dispatch(command_list, 2, 2, 2);
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transition_resource_state(command_list, textures[0],
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D3D12_RESOURCE_STATE_UNORDERED_ACCESS, D3D12_RESOURCE_STATE_COPY_SOURCE);
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get_texture_readback_with_command_list(textures[0], 0, &rb, context.queue, command_list);
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for (x = 0; x < 16; ++x)
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{
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context.pipeline_state = create_compute_pipeline_state(device, context.root_signature,
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shader_bytecode(ID3D10Blob_GetBufferPointer(cs_code), ID3D10Blob_GetBufferSize(cs_code)));
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ID3D12GraphicsCommandList_SetPipelineState(command_list, context.pipeline_state);
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ID3D12GraphicsCommandList_SetComputeRootSignature(command_list, context.root_signature);
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ID3D12GraphicsCommandList_SetComputeRootDescriptorTable(command_list,
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0, get_gpu_descriptor_handle(&context, heap, 0));
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ID3D12GraphicsCommandList_Dispatch(command_list, 2, 2, 2);
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transition_resource_state(command_list, textures[0],
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D3D12_RESOURCE_STATE_UNORDERED_ACCESS, D3D12_RESOURCE_STATE_COPY_SOURCE);
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get_texture_readback_with_command_list(textures[0], 0, &rb, context.queue, command_list);
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for (x = 0; x < 16; ++x)
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for (y = 0; y < 8; ++y)
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{
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for (y = 0; y < 8; ++y)
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for (z = 0; z < 8; ++z)
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{
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for (z = 0; z < 8; ++z)
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{
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const struct uvec4 *v = get_readback_data(&rb.rb, x, y, z, sizeof(struct uvec4));
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struct uvec4 expect = {x / 5, y / 3, z / 2, 1};
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const struct uvec4 *v = get_readback_data(&rb.rb, x, y, z, sizeof(struct uvec4));
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struct uvec4 expect = {x / 5, y / 3, z / 2, 1};
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if (x >= 10 || y >= 6 || z >= 4)
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memset(&expect, 0, sizeof(expect));
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if (x >= 10 || y >= 6 || z >= 4)
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memset(&expect, 0, sizeof(expect));
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ok(compare_uvec4(v, &expect), "Got {%u, %u, %u, %u} at (%u, %u, %u).\n",
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v->x, v->y, v->z, v->w, x, y, z);
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}
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ok(compare_uvec4(v, &expect), "Got {%u, %u, %u, %u} at (%u, %u, %u).\n",
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v->x, v->y, v->z, v->w, x, y, z);
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}
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}
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release_resource_readback(&rb);
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reset_command_list(command_list, context.allocator);
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transition_resource_state(command_list, textures[1],
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D3D12_RESOURCE_STATE_UNORDERED_ACCESS, D3D12_RESOURCE_STATE_COPY_SOURCE);
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get_texture_readback_with_command_list(textures[1], 0, &rb, context.queue, command_list);
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for (x = 0; x < 16; ++x)
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{
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for (y = 0; y < 8; ++y)
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{
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for (z = 0; z < 8; ++z)
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{
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const struct uvec4 *v = get_readback_data(&rb.rb, x, y, z, sizeof(struct uvec4));
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struct uvec4 expect = {x % 5, y % 3, z % 2, 2};
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if (x >= 10 || y >= 6 || z >= 4)
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memset(&expect, 0, sizeof(expect));
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ok(compare_uvec4(v, &expect), "Got {%u, %u, %u, %u} at (%u, %u, %u).\n",
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v->x, v->y, v->z, v->w, x, y, z);
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}
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}
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}
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release_resource_readback(&rb);
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reset_command_list(command_list, context.allocator);
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transition_resource_state(command_list, textures[2],
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D3D12_RESOURCE_STATE_UNORDERED_ACCESS, D3D12_RESOURCE_STATE_COPY_SOURCE);
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get_texture_readback_with_command_list(textures[2], 0, &rb, context.queue, command_list);
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for (x = 0; x < 16; ++x)
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{
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for (y = 0; y < 8; ++y)
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{
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for (z = 0; z < 8; ++z)
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{
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const struct uvec4 *v = get_readback_data(&rb.rb, x, y, z, sizeof(struct uvec4));
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struct uvec4 expect = {x, y, z, 3};
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if (x >= 10 || y >= 6 || z >= 4)
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memset(&expect, 0, sizeof(expect));
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ok(compare_uvec4(v, &expect), "Got {%u, %u, %u, %u} at (%u, %u, %u).\n",
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v->x, v->y, v->z, v->w, x, y, z);
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}
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}
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}
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release_resource_readback(&rb);
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reset_command_list(command_list, context.allocator);
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}
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release_resource_readback(&rb);
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reset_command_list(command_list, context.allocator);
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transition_resource_state(command_list, textures[1],
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D3D12_RESOURCE_STATE_UNORDERED_ACCESS, D3D12_RESOURCE_STATE_COPY_SOURCE);
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get_texture_readback_with_command_list(textures[1], 0, &rb, context.queue, command_list);
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for (x = 0; x < 16; ++x)
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{
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for (y = 0; y < 8; ++y)
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{
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for (z = 0; z < 8; ++z)
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{
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const struct uvec4 *v = get_readback_data(&rb.rb, x, y, z, sizeof(struct uvec4));
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struct uvec4 expect = {x % 5, y % 3, z % 2, 2};
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if (x >= 10 || y >= 6 || z >= 4)
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memset(&expect, 0, sizeof(expect));
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ok(compare_uvec4(v, &expect), "Got {%u, %u, %u, %u} at (%u, %u, %u).\n",
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v->x, v->y, v->z, v->w, x, y, z);
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}
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}
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}
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release_resource_readback(&rb);
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reset_command_list(command_list, context.allocator);
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transition_resource_state(command_list, textures[2],
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D3D12_RESOURCE_STATE_UNORDERED_ACCESS, D3D12_RESOURCE_STATE_COPY_SOURCE);
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get_texture_readback_with_command_list(textures[2], 0, &rb, context.queue, command_list);
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for (x = 0; x < 16; ++x)
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{
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for (y = 0; y < 8; ++y)
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{
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for (z = 0; z < 8; ++z)
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{
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const struct uvec4 *v = get_readback_data(&rb.rb, x, y, z, sizeof(struct uvec4));
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struct uvec4 expect = {x, y, z, 3};
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if (x >= 10 || y >= 6 || z >= 4)
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memset(&expect, 0, sizeof(expect));
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ok(compare_uvec4(v, &expect), "Got {%u, %u, %u, %u} at (%u, %u, %u).\n",
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v->x, v->y, v->z, v->w, x, y, z);
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}
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}
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}
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release_resource_readback(&rb);
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reset_command_list(command_list, context.allocator);
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for (i = 0; i < 3; ++i)
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ID3D12Resource_Release(textures[i]);
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