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vkd3d-shader: Implement DEQ instruction.
Source modifiers and immediate constants are not supported. Signed-off-by: Conor McCarthy <cmccarthy@codeweavers.com> Signed-off-by: Henri Verbeet <hverbeet@codeweavers.com> Signed-off-by: Alexandre Julliard <julliard@winehq.org>
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@ -310,6 +310,7 @@ enum vkd3d_sm4_opcode
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VKD3D_SM5_OP_IMM_ATOMIC_UMAX = 0xbc,
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VKD3D_SM5_OP_IMM_ATOMIC_UMIN = 0xbd,
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VKD3D_SM5_OP_SYNC = 0xbe,
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VKD3D_SM5_OP_DEQ = 0xc3,
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VKD3D_SM5_OP_EVAL_SAMPLE_INDEX = 0xcc,
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VKD3D_SM5_OP_EVAL_CENTROID = 0xcd,
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VKD3D_SM5_OP_DCL_GS_INSTANCES = 0xce,
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@ -1011,6 +1012,7 @@ static void shader_sm5_read_sync(struct vkd3d_shader_instruction *ins,
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}
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/*
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* d -> VKD3D_DATA_DOUBLE
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* f -> VKD3D_DATA_FLOAT
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* i -> VKD3D_DATA_INT
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* u -> VKD3D_DATA_UINT
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@ -1247,6 +1249,7 @@ static const struct vkd3d_sm4_opcode_info opcode_table[] =
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{VKD3D_SM5_OP_IMM_ATOMIC_UMIN, VKD3DSIH_IMM_ATOMIC_UMIN, "uU", "iu"},
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{VKD3D_SM5_OP_SYNC, VKD3DSIH_SYNC, "", "",
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shader_sm5_read_sync},
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{VKD3D_SM5_OP_DEQ, VKD3DSIH_DEQ, "u", "dd"},
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{VKD3D_SM5_OP_EVAL_SAMPLE_INDEX, VKD3DSIH_EVAL_SAMPLE_INDEX, "f", "fi"},
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{VKD3D_SM5_OP_EVAL_CENTROID, VKD3DSIH_EVAL_CENTROID, "f", "f"},
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{VKD3D_SM5_OP_DCL_GS_INSTANCES, VKD3DSIH_DCL_GS_INSTANCES, "", "",
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@ -1338,6 +1341,8 @@ static enum vkd3d_data_type map_data_type(char t)
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{
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switch (t)
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{
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case 'd':
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return VKD3D_DATA_DOUBLE;
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case 'f':
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return VKD3D_DATA_FLOAT;
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case 'i':
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@ -3308,6 +3308,7 @@ static uint32_t vkd3d_dxbc_compiler_emit_load_reg(struct vkd3d_dxbc_compiler *co
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enum vkd3d_shader_component_type component_type;
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struct vkd3d_shader_register_info reg_info;
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unsigned int component_count;
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unsigned int write_mask32;
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uint32_t type_id, val_id;
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if (reg->type == VKD3DSPR_IMMCONST)
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@ -3320,14 +3321,17 @@ static uint32_t vkd3d_dxbc_compiler_emit_load_reg(struct vkd3d_dxbc_compiler *co
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type_id = vkd3d_spirv_get_type_id(builder, component_type, component_count);
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return vkd3d_spirv_build_op_undef(builder, &builder->global_stream, type_id);
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}
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assert(reg_info.component_type != VKD3D_SHADER_COMPONENT_DOUBLE);
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vkd3d_dxbc_compiler_emit_dereference_register(compiler, reg, ®_info);
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write_mask32 = (reg->data_type == VKD3D_DATA_DOUBLE) ? vkd3d_write_mask_32_from_64(write_mask) : write_mask;
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/* Intermediate value (no storage class). */
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if (reg_info.storage_class == SpvStorageClassMax)
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{
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val_id = reg_info.id;
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}
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else if (component_count == 1)
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else if (vkd3d_write_mask_component_count(write_mask32) == 1)
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{
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return vkd3d_dxbc_compiler_emit_load_scalar(compiler, reg, swizzle, write_mask, ®_info);
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}
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@ -3339,7 +3343,7 @@ static uint32_t vkd3d_dxbc_compiler_emit_load_reg(struct vkd3d_dxbc_compiler *co
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}
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val_id = vkd3d_dxbc_compiler_emit_swizzle(compiler,
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val_id, reg_info.write_mask, reg_info.component_type, swizzle, write_mask);
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val_id, reg_info.write_mask, reg_info.component_type, swizzle, write_mask32);
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if (component_type != reg_info.component_type)
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{
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@ -7066,6 +7070,7 @@ static void vkd3d_dxbc_compiler_emit_comparison_instruction(struct vkd3d_dxbc_co
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switch (instruction->handler_idx)
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{
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case VKD3DSIH_DEQ:
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case VKD3DSIH_EQ: op = SpvOpFOrdEqual; break;
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case VKD3DSIH_GE: op = SpvOpFOrdGreaterThanEqual; break;
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case VKD3DSIH_IEQ: op = SpvOpIEqual; break;
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@ -9249,6 +9254,7 @@ int vkd3d_dxbc_compiler_handle_instruction(struct vkd3d_dxbc_compiler *compiler,
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case VKD3DSIH_UDIV:
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vkd3d_dxbc_compiler_emit_udiv(compiler, instruction);
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break;
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case VKD3DSIH_DEQ:
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case VKD3DSIH_EQ:
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case VKD3DSIH_GE:
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case VKD3DSIH_IEQ:
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@ -103,6 +103,7 @@ static const char * const shader_opcode_names[] =
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/* VKD3DSIH_DEFAULT */ "default",
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/* VKD3DSIH_DEFB */ "defb",
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/* VKD3DSIH_DEFI */ "defi",
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/* VKD3DSIH_DEQ */ "deq",
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/* VKD3DSIH_DIV */ "div",
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/* VKD3DSIH_DP2 */ "dp2",
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/* VKD3DSIH_DP2ADD */ "dp2add",
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@ -190,6 +190,7 @@ enum vkd3d_shader_opcode
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VKD3DSIH_DEFAULT,
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VKD3DSIH_DEFB,
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VKD3DSIH_DEFI,
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VKD3DSIH_DEQ,
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VKD3DSIH_DIV,
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VKD3DSIH_DP2,
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VKD3DSIH_DP2ADD,
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@ -1032,6 +1033,13 @@ static inline unsigned int vkd3d_write_mask_from_component_count(unsigned int co
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return (VKD3DSP_WRITEMASK_0 << component_count) - 1;
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}
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static inline unsigned int vkd3d_write_mask_32_from_64(unsigned int write_mask64)
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{
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unsigned int write_mask32 = (write_mask64 | (write_mask64 << 1))
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& (VKD3DSP_WRITEMASK_0 | VKD3DSP_WRITEMASK_2);
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return write_mask32 | (write_mask32 << 1);
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}
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static inline unsigned int vkd3d_swizzle_get_component(DWORD swizzle,
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unsigned int idx)
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{
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@ -9879,8 +9879,8 @@ static void test_shader_instructions(void)
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{&ps_dmovc, {.d = {{1.5, 0.0}}}, {.d = {1.5, 0.0}}, true, true},
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{&ps_dmodifier, {.d = {{1.5, 0.0}}}, {.d = {1.5f, 2.5f}}, true, true},
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{&ps_dmodifier, {.d = {{-1.5, 0.0}}}, {.d = {1.5f, 1.5f}}, true, true},
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{&ps_deq, {.d = {{0.0, 0.0}}}, {{0xffffffff}}, true, true},
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{&ps_deq, {.d = {{1.0, 0.0}}}, {{0x00000000}}, true, true},
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{&ps_deq, {.d = {{0.0, 0.0}}}, {{0xffffffff}}, true},
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{&ps_deq, {.d = {{1.0, 0.0}}}, {{0x00000000}}, true},
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{&ps_dne, {.d = {{0.0, 0.0}}}, {{0x00000000}}, true, true},
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{&ps_dne, {.d = {{1.0, 0.0}}}, {{0xffffffff}}, true, true},
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{&ps_dtou, {.d = {{ -NAN}}}, {{ 0, 0 }}, true, true},
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