wine/vkd3d
0
0
Fork 0
mirror of https://gitlab.winehq.org/wine/vkd3d.git synced 2024-11-21 16:46:41 -08:00
Code Issues Packages Projects Releases Wiki Activity

vkd3d-shader/hlsl: Save COS_REDUCED and SIN_REDUCED in the vsir_program for SM1.

Browse Source
This commit is contained in:
Francisco Casas 2024-07-22 21:15:25 -04:00 committed by Henri Verbeet
parent 5db2c2a949
commit 4ed16108f0
Notes: Henri Verbeet 2024-09-11 15:33:53 +02:00 
Approved-by: Elizabeth Figura (@zfigura)
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1041
2 changed files with 63 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
libs/vkd3d-shader/d3dbc.c
View File

@ -2326,6 +2326,7 @@ static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const str
case VKD3DSIH_MIN: case VKD3DSIH_MIN:
case VKD3DSIH_MOV: case VKD3DSIH_MOV:
case VKD3DSIH_MUL: case VKD3DSIH_MUL:
case VKD3DSIH_SINCOS:
case VKD3DSIH_SLT: case VKD3DSIH_SLT:
d3dbc_write_vsir_simple_instruction(d3dbc, ins); d3dbc_write_vsir_simple_instruction(d3dbc, ins);
break; break;
@ -2420,45 +2421,6 @@ static void d3dbc_write_semantic_dcls(struct d3dbc_compiler *d3dbc)
} }
} }
static void d3dbc_write_sincos(struct d3dbc_compiler *d3dbc, enum hlsl_ir_expr_op op,
const struct hlsl_reg *dst, const struct hlsl_reg *src)
{
struct sm1_instruction instr =
{
.opcode = VKD3D_SM1_OP_SINCOS,
.dst.type = VKD3DSPR_TEMP,
.dst.writemask = dst->writemask,
.dst.reg = dst->id,
.has_dst = 1,
.srcs[0].type = VKD3DSPR_TEMP,
.srcs[0].swizzle = hlsl_swizzle_from_writemask(src->writemask),
.srcs[0].reg = src->id,
.src_count = 1,
};
if (op == HLSL_OP1_COS_REDUCED)
VKD3D_ASSERT(dst->writemask == VKD3DSP_WRITEMASK_0);
else /* HLSL_OP1_SIN_REDUCED */
VKD3D_ASSERT(dst->writemask == VKD3DSP_WRITEMASK_1);
if (d3dbc->ctx->profile->major_version < 3)
{
instr.src_count = 3;
instr.srcs[1].type = VKD3DSPR_CONST;
instr.srcs[1].swizzle = hlsl_swizzle_from_writemask(VKD3DSP_WRITEMASK_ALL);
instr.srcs[1].reg = d3dbc->ctx->d3dsincosconst1.id;
instr.srcs[2].type = VKD3DSPR_CONST;
instr.srcs[2].swizzle = hlsl_swizzle_from_writemask(VKD3DSP_WRITEMASK_ALL);
instr.srcs[2].reg = d3dbc->ctx->d3dsincosconst2.id;
}
d3dbc_write_instruction(d3dbc, &instr);
}
static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_node *instr) static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_node *instr)
{ {
struct hlsl_ir_expr *expr = hlsl_ir_expr(instr); struct hlsl_ir_expr *expr = hlsl_ir_expr(instr);
@ -2490,11 +2452,6 @@ static void d3dbc_write_expr(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
switch (expr->op) switch (expr->op)
{ {
case HLSL_OP1_COS_REDUCED:
case HLSL_OP1_SIN_REDUCED:
d3dbc_write_sincos(d3dbc, expr->op, &instr->reg, &arg1->reg);
break;
case HLSL_OP3_DP2ADD: case HLSL_OP3_DP2ADD:
d3dbc_write_dp2add(d3dbc, &instr->reg, &arg1->reg, &arg2->reg, &arg3->reg); d3dbc_write_dp2add(d3dbc, &instr->reg, &arg1->reg, &arg2->reg, &arg3->reg);
break; break;

62
libs/vkd3d-shader/hlsl_codegen.c
View File

@ -6632,6 +6632,58 @@ static void sm1_generate_vsir_instr_expr_per_component_instr_op(struct hlsl_ctx
hlsl_replace_node(instr, vsir_instr); hlsl_replace_node(instr, vsir_instr);
} }
static void sm1_generate_vsir_instr_expr_sincos(struct hlsl_ctx *ctx, struct vsir_program *program,
struct hlsl_ir_expr *expr)
{
struct vkd3d_shader_instruction_array *instructions = &program->instructions;
struct hlsl_ir_node *operand = expr->operands[0].node;
struct hlsl_ir_node *instr = &expr->node;
struct vkd3d_shader_dst_param *dst_param;
struct vkd3d_shader_src_param *src_param;
struct vkd3d_shader_instruction *ins;
struct hlsl_ir_node *vsir_instr;
unsigned int src_count = 0;
VKD3D_ASSERT(instr->reg.allocated);
src_count = (ctx->profile->major_version < 3) ? 3 : 1;
if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, VKD3DSIH_SINCOS, 1, src_count)))
return;
dst_param = &ins->dst[0];
vsir_register_init(&dst_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
dst_param->reg.idx[0].offset = instr->reg.id;
dst_param->write_mask = instr->reg.writemask;
src_param = &ins->src[0];
vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = operand->reg.id;
src_param->swizzle = sm1_generate_vsir_get_src_swizzle(operand->reg.writemask, VKD3DSP_WRITEMASK_ALL);
if (ctx->profile->major_version < 3)
{
src_param = &ins->src[1];
vsir_register_init(&src_param->reg, VKD3DSPR_CONST, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = ctx->d3dsincosconst1.id;
src_param->swizzle = VKD3D_SHADER_NO_SWIZZLE;
src_param = &ins->src[1];
vsir_register_init(&src_param->reg, VKD3DSPR_CONST, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = ctx->d3dsincosconst2.id;
src_param->swizzle = VKD3D_SHADER_NO_SWIZZLE;
}
if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, instructions->count - 1, instr->data_type,
&instr->reg, &instr->loc)))
{
ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
return;
}
list_add_before(&instr->entry, &vsir_instr->entry);
hlsl_replace_node(instr, vsir_instr);
}
static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_program *program, static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_program *program,
struct hlsl_ir_expr *expr) struct hlsl_ir_expr *expr)
{ {
@ -6641,6 +6693,11 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ABS, 0, 0, true); sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ABS, 0, 0, true);
break; break;
case HLSL_OP1_COS_REDUCED:
VKD3D_ASSERT(expr->node.reg.writemask == VKD3DSP_WRITEMASK_0);
sm1_generate_vsir_instr_expr_sincos(ctx, program, expr);
break;
case HLSL_OP1_DSX: case HLSL_OP1_DSX:
sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DSX, 0, 0, true); sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_DSX, 0, 0, true);
break; break;
@ -6673,6 +6730,11 @@ static bool sm1_generate_vsir_instr_expr(struct hlsl_ctx *ctx, struct vsir_progr
sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, VKD3DSPDM_SATURATE, true); sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_MOV, 0, VKD3DSPDM_SATURATE, true);
break; break;
case HLSL_OP1_SIN_REDUCED:
VKD3D_ASSERT(expr->node.reg.writemask == VKD3DSP_WRITEMASK_1);
sm1_generate_vsir_instr_expr_sincos(ctx, program, expr);
break;
case HLSL_OP2_ADD: case HLSL_OP2_ADD:
sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ADD, 0, 0, true); sm1_generate_vsir_instr_expr_single_instr_op(ctx, program, expr, VKD3DSIH_ADD, 0, 0, true);
break; break;