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vkd3d-shader/hlsl: Store SM4 HLSL_RESOURCE_GATHERs in the vsir program.
This commit is contained in:
parent
42ce821603
commit
4382af6e1b
Notes:
Henri Verbeet
2024-11-24 00:11:40 +01:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1276
@ -9096,6 +9096,75 @@ static bool sm4_generate_vsir_instr_sample(struct hlsl_ctx *ctx,
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return true;
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}
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static bool sm4_generate_vsir_instr_gather(struct hlsl_ctx *ctx, struct vsir_program *program,
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const struct hlsl_ir_resource_load *load, uint32_t swizzle)
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{
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const struct vkd3d_shader_version *version = &program->shader_version;
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const struct hlsl_ir_node *texel_offset = load->texel_offset.node;
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const struct hlsl_ir_node *coords = load->coords.node;
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const struct hlsl_deref *resource = &load->resource;
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const struct hlsl_deref *sampler = &load->sampler;
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const struct hlsl_ir_node *instr = &load->node;
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struct vkd3d_shader_instruction *ins;
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enum vkd3d_shader_opcode opcode;
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opcode = VKD3DSIH_GATHER4;
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if (texel_offset && !sm4_generate_vsir_validate_texel_offset_aoffimmi(texel_offset))
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{
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if (!vkd3d_shader_ver_ge(version, 5, 0))
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{
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hlsl_error(ctx, &texel_offset->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TEXEL_OFFSET,
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"Offset must resolve to integer literal in the range -8 to 7 for profiles < 5.");
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return false;
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}
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opcode = VKD3DSIH_GATHER4_PO;
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}
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if (opcode == VKD3DSIH_GATHER4)
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{
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if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, opcode, 1, 3)))
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return false;
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vsir_dst_from_hlsl_node(&ins->dst[0], ctx, instr);
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vsir_src_from_hlsl_node(&ins->src[0], ctx, coords, VKD3DSP_WRITEMASK_ALL);
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sm4_generate_vsir_encode_texel_offset_as_aoffimmi(ins, texel_offset);
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if (!sm4_generate_vsir_init_src_param_from_deref(ctx, program,
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&ins->src[1], resource, ins->dst[0].write_mask, &instr->loc))
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return false;
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if (!sm4_generate_vsir_init_src_param_from_deref(ctx, program,
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&ins->src[2], sampler, VKD3DSP_WRITEMASK_ALL, &instr->loc))
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return false;
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ins->src[2].reg.dimension = VSIR_DIMENSION_VEC4;
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ins->src[2].swizzle = swizzle;
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}
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else if (opcode == VKD3DSIH_GATHER4_PO)
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{
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if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, opcode, 1, 4)))
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return false;
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vsir_dst_from_hlsl_node(&ins->dst[0], ctx, instr);
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vsir_src_from_hlsl_node(&ins->src[0], ctx, coords, VKD3DSP_WRITEMASK_ALL);
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vsir_src_from_hlsl_node(&ins->src[1], ctx, texel_offset, VKD3DSP_WRITEMASK_ALL);
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if (!sm4_generate_vsir_init_src_param_from_deref(ctx, program,
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&ins->src[2], resource, ins->dst[0].write_mask, &instr->loc))
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return false;
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if (!sm4_generate_vsir_init_src_param_from_deref(ctx, program,
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&ins->src[3], sampler, VKD3DSP_WRITEMASK_ALL, &instr->loc))
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return false;
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ins->src[3].reg.dimension = VSIR_DIMENSION_VEC4;
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ins->src[3].swizzle = swizzle;
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}
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else
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{
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vkd3d_unreachable();
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}
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return true;
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}
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static bool sm4_generate_vsir_instr_resource_load(struct hlsl_ctx *ctx,
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struct vsir_program *program, const struct hlsl_ir_resource_load *load)
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{
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@ -9126,6 +9195,18 @@ static bool sm4_generate_vsir_instr_resource_load(struct hlsl_ctx *ctx,
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VKD3D_ASSERT(load->sampler.var);
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return sm4_generate_vsir_instr_sample(ctx, program, load);
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case HLSL_RESOURCE_GATHER_RED:
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return sm4_generate_vsir_instr_gather(ctx, program, load, VKD3D_SHADER_SWIZZLE(X, X, X, X));
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case HLSL_RESOURCE_GATHER_GREEN:
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return sm4_generate_vsir_instr_gather(ctx, program, load, VKD3D_SHADER_SWIZZLE(Y, Y, Y, Y));
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case HLSL_RESOURCE_GATHER_BLUE:
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return sm4_generate_vsir_instr_gather(ctx, program, load, VKD3D_SHADER_SWIZZLE(Z, Z, Z, Z));
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case HLSL_RESOURCE_GATHER_ALPHA:
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return sm4_generate_vsir_instr_gather(ctx, program, load, VKD3D_SHADER_SWIZZLE(W, W, W, W));
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case HLSL_RESOURCE_SAMPLE_PROJ:
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vkd3d_unreachable();
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@ -4652,33 +4652,6 @@ static void write_sm4_instruction(const struct tpf_compiler *tpf, const struct s
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sm4_update_stat_counters(tpf, instr);
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}
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static bool encode_texel_offset_as_aoffimmi(struct sm4_instruction *instr,
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const struct hlsl_ir_node *texel_offset)
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{
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struct sm4_instruction_modifier modif;
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struct hlsl_ir_constant *offset;
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if (!texel_offset || texel_offset->type != HLSL_IR_CONSTANT)
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return false;
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offset = hlsl_ir_constant(texel_offset);
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modif.type = VKD3D_SM4_MODIFIER_AOFFIMMI;
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modif.u.aoffimmi.u = offset->value.u[0].i;
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modif.u.aoffimmi.v = 0;
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modif.u.aoffimmi.w = 0;
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if (offset->node.data_type->dimx > 1)
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modif.u.aoffimmi.v = offset->value.u[1].i;
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if (offset->node.data_type->dimx > 2)
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modif.u.aoffimmi.w = offset->value.u[2].i;
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if (modif.u.aoffimmi.u < -8 || modif.u.aoffimmi.u > 7
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|| modif.u.aoffimmi.v < -8 || modif.u.aoffimmi.v > 7
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|| modif.u.aoffimmi.w < -8 || modif.u.aoffimmi.w > 7)
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return false;
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instr->modifiers[instr->modifier_count++] = modif;
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return true;
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}
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static void write_sm4_dcl_constant_buffer(const struct tpf_compiler *tpf, const struct hlsl_buffer *cbuffer)
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{
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size_t size = (cbuffer->used_size + 3) / 4;
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@ -5167,53 +5140,8 @@ static void write_sm4_loop(struct tpf_compiler *tpf, const struct hlsl_ir_loop *
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write_sm4_instruction(tpf, &instr);
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}
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static void write_sm4_gather(const struct tpf_compiler *tpf, const struct hlsl_ir_node *dst,
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const struct hlsl_deref *resource, const struct hlsl_deref *sampler,
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const struct hlsl_ir_node *coords, uint32_t swizzle, const struct hlsl_ir_node *texel_offset)
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{
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const struct vkd3d_shader_version *version = &tpf->program->shader_version;
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struct vkd3d_shader_src_param *src;
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struct sm4_instruction instr;
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memset(&instr, 0, sizeof(instr));
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instr.opcode = VKD3D_SM4_OP_GATHER4;
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sm4_dst_from_node(&instr.dsts[0], dst);
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instr.dst_count = 1;
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sm4_src_from_node(tpf, &instr.srcs[instr.src_count++], coords, VKD3DSP_WRITEMASK_ALL);
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if (texel_offset)
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{
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if (!encode_texel_offset_as_aoffimmi(&instr, texel_offset))
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{
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if (!vkd3d_shader_ver_ge(version, 5, 0))
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{
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hlsl_error(tpf->ctx, &texel_offset->loc, VKD3D_SHADER_ERROR_HLSL_INVALID_TEXEL_OFFSET,
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"Offset must resolve to integer literal in the range -8 to 7 for profiles < 5.");
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return;
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}
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instr.opcode = VKD3D_SM5_OP_GATHER4_PO;
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sm4_src_from_node(tpf, &instr.srcs[instr.src_count++], texel_offset, VKD3DSP_WRITEMASK_ALL);
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}
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}
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sm4_src_from_deref(tpf, &instr.srcs[instr.src_count++], resource, instr.dsts[0].write_mask, &instr);
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src = &instr.srcs[instr.src_count++];
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sm4_src_from_deref(tpf, src, sampler, VKD3DSP_WRITEMASK_ALL, &instr);
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src->reg.dimension = VSIR_DIMENSION_VEC4;
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src->swizzle = swizzle;
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write_sm4_instruction(tpf, &instr);
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}
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static void write_sm4_resource_load(const struct tpf_compiler *tpf, const struct hlsl_ir_resource_load *load)
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{
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const struct hlsl_ir_node *texel_offset = load->texel_offset.node;
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const struct hlsl_ir_node *coords = load->coords.node;
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if (load->sampler.var && !load->sampler.var->is_uniform)
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{
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hlsl_fixme(tpf->ctx, &load->node.loc, "Sample using non-uniform sampler variable.");
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@ -5228,26 +5156,6 @@ static void write_sm4_resource_load(const struct tpf_compiler *tpf, const struct
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switch (load->load_type)
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{
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case HLSL_RESOURCE_GATHER_RED:
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write_sm4_gather(tpf, &load->node, &load->resource, &load->sampler, coords,
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VKD3D_SHADER_SWIZZLE(X, X, X, X), texel_offset);
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break;
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case HLSL_RESOURCE_GATHER_GREEN:
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write_sm4_gather(tpf, &load->node, &load->resource, &load->sampler, coords,
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VKD3D_SHADER_SWIZZLE(Y, Y, Y, Y), texel_offset);
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break;
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case HLSL_RESOURCE_GATHER_BLUE:
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write_sm4_gather(tpf, &load->node, &load->resource, &load->sampler, coords,
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VKD3D_SHADER_SWIZZLE(Z, Z, Z, Z), texel_offset);
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break;
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case HLSL_RESOURCE_GATHER_ALPHA:
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write_sm4_gather(tpf, &load->node, &load->resource, &load->sampler, coords,
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VKD3D_SHADER_SWIZZLE(W, W, W, W), texel_offset);
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break;
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case HLSL_RESOURCE_SAMPLE_INFO:
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write_sm4_sampleinfo(tpf, load);
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break;
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@ -5256,6 +5164,10 @@ static void write_sm4_resource_load(const struct tpf_compiler *tpf, const struct
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write_sm4_resinfo(tpf, load);
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break;
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case HLSL_RESOURCE_GATHER_RED:
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case HLSL_RESOURCE_GATHER_GREEN:
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case HLSL_RESOURCE_GATHER_BLUE:
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case HLSL_RESOURCE_GATHER_ALPHA:
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case HLSL_RESOURCE_SAMPLE:
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case HLSL_RESOURCE_SAMPLE_CMP:
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case HLSL_RESOURCE_SAMPLE_CMP_LZ:
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@ -5432,6 +5344,8 @@ static void tpf_handle_instruction(struct tpf_compiler *tpf, const struct vkd3d_
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case VKD3DSIH_FRC:
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case VKD3DSIH_FTOI:
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case VKD3DSIH_FTOU:
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case VKD3DSIH_GATHER4:
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case VKD3DSIH_GATHER4_PO:
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case VKD3DSIH_GEO:
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case VKD3DSIH_IADD:
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case VKD3DSIH_IEQ:
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