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vkd3d-shader/hlsl: Convert descriptor registers to pre-5.1 form in the TPF writer.

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Rather than in the HLSL writer. This way we output vsir consistent with the vsir
we read, and the vsir that the backends expect [bringing us one step closer to
being able to feed the HLSL frontend directly into the individual backends.]
This commit is contained in:
Elizabeth Figura
2025-06-23 18:21:39 -05:00
committed by Henri Verbeet
parent 3a4f95aca6
commit 41cacba5ce
Notes: Henri Verbeet 2025-06-25 17:08:41 +02:00 
Approved-by: Giovanni Mascellani (@giomasce)
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1597
2 changed files with 53 additions and 49 deletions
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65
libs/vkd3d-shader/hlsl_codegen.c
View File

@@ -8493,18 +8493,10 @@ static bool sm4_generate_vsir_reg_from_deref(struct hlsl_ctx *ctx, struct vsir_p
{
reg->type = VKD3DSPR_RESOURCE;
reg->dimension = VSIR_DIMENSION_VEC4;
if (vkd3d_shader_ver_ge(version, 5, 1))
{
reg->idx[0].offset = var->regs[HLSL_REGSET_TEXTURES].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_TEXTURES].index; /* FIXME: array index */
reg->idx_count = 2;
}
else
{
reg->idx[0].offset = var->regs[HLSL_REGSET_TEXTURES].index;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 1;
}
reg->idx[0].offset = var->regs[HLSL_REGSET_TEXTURES].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_TEXTURES].index;
reg->idx[1].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 2;
VKD3D_ASSERT(regset == HLSL_REGSET_TEXTURES);
*writemask = VKD3DSP_WRITEMASK_ALL;
}
@@ -8512,18 +8504,10 @@ static bool sm4_generate_vsir_reg_from_deref(struct hlsl_ctx *ctx, struct vsir_p
{
reg->type = VKD3DSPR_UAV;
reg->dimension = VSIR_DIMENSION_VEC4;
if (vkd3d_shader_ver_ge(version, 5, 1))
{
reg->idx[0].offset = var->regs[HLSL_REGSET_UAVS].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_UAVS].index; /* FIXME: array index */
reg->idx_count = 2;
}
else
{
reg->idx[0].offset = var->regs[HLSL_REGSET_UAVS].index;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 1;
}
reg->idx[0].offset = var->regs[HLSL_REGSET_UAVS].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_UAVS].index;
reg->idx[1].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 2;
VKD3D_ASSERT(regset == HLSL_REGSET_UAVS);
*writemask = VKD3DSP_WRITEMASK_ALL;
}
@@ -8531,18 +8515,10 @@ static bool sm4_generate_vsir_reg_from_deref(struct hlsl_ctx *ctx, struct vsir_p
{
reg->type = VKD3DSPR_SAMPLER;
reg->dimension = VSIR_DIMENSION_NONE;
if (vkd3d_shader_ver_ge(version, 5, 1))
{
reg->idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_SAMPLERS].index; /* FIXME: array index */
reg->idx_count = 2;
}
else
{
reg->idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].index;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 1;
}
reg->idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_SAMPLERS].index;
reg->idx[1].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 2;
VKD3D_ASSERT(regset == HLSL_REGSET_SAMPLERS);
*writemask = VKD3DSP_WRITEMASK_ALL;
}
@@ -8561,19 +8537,10 @@ static bool sm4_generate_vsir_reg_from_deref(struct hlsl_ctx *ctx, struct vsir_p
VKD3D_ASSERT(data_type->class <= HLSL_CLASS_VECTOR);
reg->type = VKD3DSPR_CONSTBUFFER;
reg->dimension = VSIR_DIMENSION_VEC4;
if (vkd3d_shader_ver_ge(version, 5, 1))
{
reg->idx[0].offset = var->buffer->reg.id;
reg->idx[1].offset = var->buffer->reg.index; /* FIXME: array index */
reg->idx[2].offset = offset / 4;
reg->idx_count = 3;
}
else
{
reg->idx[0].offset = var->buffer->reg.index;
reg->idx[1].offset = offset / 4;
reg->idx_count = 2;
}
reg->idx[0].offset = var->buffer->reg.id;
reg->idx[1].offset = var->buffer->reg.index; /* FIXME: array index */
reg->idx[2].offset = offset / 4;
reg->idx_count = 3;
if (deref->rel_offset.node)
{

37
libs/vkd3d-shader/tpf.c
View File

@@ -4046,6 +4046,39 @@ static void tpf_write_dcl_vertices_out(const struct tpf_compiler *tpf, unsigned
write_sm4_instruction(tpf, &instr);
}
/* Descriptor registers are stored in shader model 5.1 format regardless
* of the program's version. Convert them to the 4.0 format if necessary. */
static void rewrite_descriptor_register(const struct tpf_compiler *tpf, struct vkd3d_shader_register *reg)
{
if (vkd3d_shader_ver_ge(&tpf->program->shader_version, 5, 1))
return;
switch (reg->type)
{
case VKD3DSPR_CONSTBUFFER:
reg->idx[0] = reg->idx[1];
reg->idx[1] = reg->idx[2];
reg->idx_count = 2;
break;
case VKD3DSPR_RESOURCE:
case VKD3DSPR_SAMPLER:
case VKD3DSPR_UAV:
reg->idx[0] = reg->idx[1];
reg->idx_count = 1;
break;
default:
break;
}
for (unsigned int i = 0; i < reg->idx_count; ++i)
{
if (reg->idx[i].rel_addr)
rewrite_descriptor_register(tpf, &reg->idx[i].rel_addr->reg);
}
}
static void tpf_simple_instruction(struct tpf_compiler *tpf, const struct vkd3d_shader_instruction *ins)
{
struct sm4_instruction_modifier *modifier;
@@ -4082,6 +4115,7 @@ static void tpf_simple_instruction(struct tpf_compiler *tpf, const struct vkd3d_
for (unsigned int i = 0; i < ins->dst_count; ++i)
{
instr.dsts[i] = ins->dst[i];
rewrite_descriptor_register(tpf, &instr.dsts[i].reg);
if (instr.dsts[i].modifiers & VKD3DSPDM_SATURATE)
{
@@ -4092,7 +4126,10 @@ static void tpf_simple_instruction(struct tpf_compiler *tpf, const struct vkd3d_
}
}
for (unsigned int i = 0; i < ins->src_count; ++i)
{
instr.srcs[i] = ins->src[i];
rewrite_descriptor_register(tpf, &instr.srcs[i].reg);
}
if (ins->texel_offset.u || ins->texel_offset.v || ins->texel_offset.w)
{