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vkd3d-shader/ir: Check that COVERAGE registers have dimension VEC4.

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Also fix the HLSL compiler and DXIL parser to emit them accordingly.
This commit is contained in:
Giovanni Mascellani
2025-07-18 18:45:43 +02:00
committed by Henri Verbeet
parent ee0447b973
commit 3d23ef6bf8
Notes: Henri Verbeet 2025-07-21 12:36:12 +02:00 
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1629
3 changed files with 8 additions and 10 deletions
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12
libs/vkd3d-shader/dxil.c
View File

@@ -5195,7 +5195,7 @@ static void sm6_parser_dcl_register_builtin(struct sm6_parser *sm6, enum vkd3d_s
}
static void sm6_parser_emit_dx_input_register_mov(struct sm6_parser *sm6, struct vkd3d_shader_instruction *ins,
enum vkd3d_shader_register_type reg_type, enum vsir_data_type data_type)
enum vkd3d_shader_register_type reg_type, enum vsir_data_type data_type, bool scalar)
{
struct vkd3d_shader_src_param *src_param;
@@ -5205,6 +5205,8 @@ static void sm6_parser_emit_dx_input_register_mov(struct sm6_parser *sm6, struct
return;
sm6_parser_dcl_register_builtin(sm6, VSIR_OP_DCL_INPUT, reg_type, data_type, 1);
vsir_register_init(&src_param->reg, reg_type, data_type, 0);
if (!scalar)
src_param->reg.dimension = VSIR_DIMENSION_VEC4;
src_param_init(src_param);
instruction_dst_param_init_ssa_scalar(ins, sm6);
@@ -5213,7 +5215,7 @@ static void sm6_parser_emit_dx_input_register_mov(struct sm6_parser *sm6, struct
static void sm6_parser_emit_dx_coverage(struct sm6_parser *sm6, enum dx_intrinsic_opcode op,
const struct sm6_value **operands, struct function_emission_state *state)
{
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, VKD3DSPR_COVERAGE, VKD3D_DATA_UINT);
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, VKD3DSPR_COVERAGE, VKD3D_DATA_UINT, false);
}
static const struct sm6_descriptor_info *sm6_parser_get_descriptor(struct sm6_parser *sm6,
@@ -5711,13 +5713,13 @@ static void sm6_parser_emit_dx_make_double(struct sm6_parser *sm6, enum dx_intri
static void sm6_parser_emit_dx_output_control_point_id(struct sm6_parser *sm6, enum dx_intrinsic_opcode op,
const struct sm6_value **operands, struct function_emission_state *state)
{
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, VKD3DSPR_OUTPOINTID, VKD3D_DATA_UINT);
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, VKD3DSPR_OUTPOINTID, VKD3D_DATA_UINT, true);
}
static void sm6_parser_emit_dx_primitive_id(struct sm6_parser *sm6, enum dx_intrinsic_opcode op,
const struct sm6_value **operands, struct function_emission_state *state)
{
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, VKD3DSPR_PRIMID, VKD3D_DATA_UINT);
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, VKD3DSPR_PRIMID, VKD3D_DATA_UINT, true);
}
static enum vkd3d_shader_opcode dx_map_quad_op(enum dxil_quad_op_kind op)
@@ -6533,7 +6535,7 @@ static void sm6_parser_emit_dx_wave_builtin(struct sm6_parser *sm6, enum dx_intr
vkd3d_unreachable();
}
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, type, VKD3D_DATA_UINT);
sm6_parser_emit_dx_input_register_mov(sm6, state->ins, type, VKD3D_DATA_UINT, true);
}
struct sm6_dx_opcode_info

5
libs/vkd3d-shader/ir.c
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@@ -9543,6 +9543,7 @@ static void vsir_validate_register(struct validation_context *ctx,
register_validation_data[] =
{
[VKD3DSPR_LOCALTHREADINDEX] = {true, 0, VSIR_DIMENSION_VEC4},
[VKD3DSPR_COVERAGE] = {true, 0, VSIR_DIMENSION_VEC4},
};
const struct register_validation_data *validation_data;
@@ -9695,10 +9696,6 @@ static void vsir_validate_register(struct validation_context *ctx,
vsir_validate_register_without_indices(ctx, reg);
break;
case VKD3DSPR_COVERAGE:
vsir_validate_register_without_indices(ctx, reg);
break;
case VKD3DSPR_SAMPLEMASK:
vsir_validate_register_without_indices(ctx, reg);
break;

1
libs/vkd3d-shader/tpf.c
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@@ -2237,7 +2237,6 @@ bool shader_sm4_is_scalar_register(const struct vkd3d_shader_register *reg)
{
switch (reg->type)
{
case VKD3DSPR_COVERAGE:
case VKD3DSPR_DEPTHOUT:
case VKD3DSPR_DEPTHOUTGE:
case VKD3DSPR_DEPTHOUTLE: