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vkd3d-shader/d3dbc: Lower TEXCOORD instructions.

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This commit is contained in:
Elizabeth Figura
2025-04-07 17:20:17 -05:00
committed by Henri Verbeet
parent 5706834b37
commit 32e64cafa5
Notes: Henri Verbeet 2025-09-17 12:56:28 +02:00 
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1688
2 changed files with 49 additions and 1 deletions
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35
libs/vkd3d-shader/ir.c
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@@ -1854,6 +1854,35 @@ static enum vkd3d_result vsir_program_lower_tex(struct vsir_program *program, st
return VKD3D_OK; return VKD3D_OK;
} }
static enum vkd3d_result vsir_program_lower_texcoord(struct vsir_program *program,
struct vkd3d_shader_instruction *ins)
{
unsigned int idx = ins->dst[0].reg.idx[0].offset;
struct vkd3d_shader_src_param *srcs;
/* texcoord t# -> mov_sat t#, t#
* Note that the t# destination will subsequently be turned into a temp. */
/* We run before I/O normalization. */
VKD3D_ASSERT(program->normalisation_level < VSIR_NORMALISED_SM6);
if (!(srcs = shader_src_param_allocator_get(&program->instructions.src_params, 1)))
return VKD3D_ERROR_OUT_OF_MEMORY;
vsir_src_param_init(&srcs[0], VKD3DSPR_TEXTURE, VSIR_DATA_F32, 1);
srcs[0].reg.idx[0].offset = idx;
srcs[0].reg.dimension = VSIR_DIMENSION_VEC4;
srcs[0].swizzle = VKD3D_SHADER_NO_SWIZZLE;
ins->dst[0].modifiers |= VKD3DSPDM_SATURATE;
ins->opcode = VSIR_OP_MOV;
ins->src = srcs;
ins->src_count = 1;
return VKD3D_OK;
}
static enum vkd3d_result vsir_program_lower_dcl_input(struct vsir_program *program, static enum vkd3d_result vsir_program_lower_dcl_input(struct vsir_program *program,
struct vkd3d_shader_instruction *ins, struct vsir_transformation_context *ctx) struct vkd3d_shader_instruction *ins, struct vsir_transformation_context *ctx)
{ {
@@ -1946,6 +1975,11 @@ static enum vkd3d_result vsir_program_lower_d3dbc_instructions(struct vsir_progr
ret = vsir_program_lower_sm1_sincos(program, &it); ret = vsir_program_lower_sm1_sincos(program, &it);
break; break;
case VSIR_OP_TEXCOORD:
if ((ret = vsir_program_lower_texcoord(program, ins)) < 0)
return ret;
break;
case VSIR_OP_TEXCRD: case VSIR_OP_TEXCRD:
ret = vsir_program_lower_texcrd(program, ins, message_context); ret = vsir_program_lower_texcrd(program, ins, message_context);
break; break;
@@ -1977,7 +2011,6 @@ static enum vkd3d_result vsir_program_lower_d3dbc_instructions(struct vsir_progr
case VSIR_OP_TEXBEM: case VSIR_OP_TEXBEM:
case VSIR_OP_TEXBEML: case VSIR_OP_TEXBEML:
case VSIR_OP_TEXCOORD:
case VSIR_OP_TEXDEPTH: case VSIR_OP_TEXDEPTH:
case VSIR_OP_TEXDP3: case VSIR_OP_TEXDP3:
case VSIR_OP_TEXDP3TEX: case VSIR_OP_TEXDP3TEX:

15
tests/hlsl/ps1-sampler.shader_test
View File

@@ -49,6 +49,21 @@ void main(inout float4 pos : position, out float4 tex : texcoord)
tex = pos; tex = pos;
} }
[pixel shader d3dbc-hex]
% TODO: Convert to assembly or HLSL.
ffff0101 % ps_1_1
00000051 a00f0000 3e4ccccd 3e4ccccd 3e4ccccd 3e4ccccd % def c0, 0.2, 0.2, 0.2, 0.2
00000040 b00f0000 % texcoord t0
00000002 800f0000 b0e40000 a0e40000 % add r0, t0, c0
0000ffff % end
[test]
draw quad
probe (160, 120) f32(0.2, 0.7, 0.2, 1) 32
probe (480, 120) f32(0.7, 0.7, 0.2, 1) 32
probe (160, 360) f32(0.2, 0.2, 0.2, 1) 8
probe (480, 360) f32(0.7, 0.2, 0.2, 1) 8
[pixel shader d3dbc-hex] [pixel shader d3dbc-hex]
% TODO: Convert to assembly or HLSL. % TODO: Convert to assembly or HLSL.
ffff0104 % ps_1_4 ffff0104 % ps_1_4