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vkd3d-shader/ir: Validate the register type for DCL_OUTPUT_SIV instructions.

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Giovanni Mascellani 2024-11-21 23:34:11 +01:00 committed by Henri Verbeet
parent 3832e38ce0
commit 2c3a7b0dd9
Notes: Henri Verbeet 2024-11-25 21:02:53 +01:00 
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1279
1 changed files with 17 additions and 0 deletions
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17
libs/vkd3d-shader/ir.c
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@ -8130,6 +8130,22 @@ static void vsir_validate_dcl_output_control_point_count(struct validation_conte
instruction->declaration.count); instruction->declaration.count);
} }
static void vsir_validate_dcl_output_siv(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction)
{
switch (instruction->declaration.register_semantic.reg.reg.type)
{
case VKD3DSPR_OUTPUT:
case VKD3DSPR_PATCHCONST:
break;
default:
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE,
"Invalid register type %#x in instruction DCL_OUTPUT_SIV.",
instruction->declaration.register_semantic.reg.reg.type);
}
}
static void vsir_validate_dcl_output_topology(struct validation_context *ctx, static void vsir_validate_dcl_output_topology(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction) const struct vkd3d_shader_instruction *instruction)
{ {
@ -8435,6 +8451,7 @@ static const struct vsir_validator_instruction_desc vsir_validator_instructions[
[VKD3DSIH_DCL_INPUT_SIV] = {0, 0, vsir_validate_dcl_input_siv}, [VKD3DSIH_DCL_INPUT_SIV] = {0, 0, vsir_validate_dcl_input_siv},
[VKD3DSIH_DCL_OUTPUT] = {0, 0, vsir_validate_dcl_output}, [VKD3DSIH_DCL_OUTPUT] = {0, 0, vsir_validate_dcl_output},
[VKD3DSIH_DCL_OUTPUT_CONTROL_POINT_COUNT] = {0, 0, vsir_validate_dcl_output_control_point_count}, [VKD3DSIH_DCL_OUTPUT_CONTROL_POINT_COUNT] = {0, 0, vsir_validate_dcl_output_control_point_count},
[VKD3DSIH_DCL_OUTPUT_SIV] = {0, 0, vsir_validate_dcl_output_siv},
[VKD3DSIH_DCL_OUTPUT_TOPOLOGY] = {0, 0, vsir_validate_dcl_output_topology}, [VKD3DSIH_DCL_OUTPUT_TOPOLOGY] = {0, 0, vsir_validate_dcl_output_topology},
[VKD3DSIH_DCL_TEMPS] = {0, 0, vsir_validate_dcl_temps}, [VKD3DSIH_DCL_TEMPS] = {0, 0, vsir_validate_dcl_temps},
[VKD3DSIH_DCL_TESSELLATOR_DOMAIN] = {0, 0, vsir_validate_dcl_tessellator_domain}, [VKD3DSIH_DCL_TESSELLATOR_DOMAIN] = {0, 0, vsir_validate_dcl_tessellator_domain},