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vkd3d-shader: Write SM5.1 register indices.

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Separate ID and index. Allocate IDs for all external resources (but ignore them
for shader models other than 5).
This commit is contained in:
Elizabeth Figura
2023-08-29 12:13:35 -05:00
committed by Henri Verbeet
parent 19a13740de
commit 28a5e23814
Notes: Henri Verbeet 2024-06-11 17:09:29 +02:00 
Approved-by: Francisco Casas (@fcasas)
Approved-by: Giovanni Mascellani (@giomasce)
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/865
4 changed files with 156 additions and 45 deletions
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126
libs/vkd3d-shader/tpf.c
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@@ -3185,7 +3185,7 @@ struct extern_resource
bool is_user_packed;
enum hlsl_regset regset;
unsigned int id, bind_count;
unsigned int id, index, bind_count;
};
static int sm4_compare_extern_resources(const void *a, const void *b)
@@ -3197,7 +3197,7 @@ static int sm4_compare_extern_resources(const void *a, const void *b)
if ((r = vkd3d_u32_compare(aa->regset, bb->regset)))
return r;
return vkd3d_u32_compare(aa->id, bb->id);
return vkd3d_u32_compare(aa->index, bb->index);
}
static void sm4_free_extern_resources(struct extern_resource *extern_resources, unsigned int count)
@@ -3281,7 +3281,8 @@ static struct extern_resource *sm4_get_extern_resources(struct hlsl_ctx *ctx, un
extern_resources[*count].is_user_packed = !!var->reg_reservation.reg_type;
extern_resources[*count].regset = regset;
extern_resources[*count].id = var->regs[regset].id + regset_offset;
extern_resources[*count].id = var->regs[regset].id;
extern_resources[*count].index = var->regs[regset].index + regset_offset;
extern_resources[*count].bind_count = 1;
++*count;
@@ -3324,6 +3325,7 @@ static struct extern_resource *sm4_get_extern_resources(struct hlsl_ctx *ctx, un
extern_resources[*count].regset = r;
extern_resources[*count].id = var->regs[r].id;
extern_resources[*count].index = var->regs[r].index;
extern_resources[*count].bind_count = var->bind_count[r];
++*count;
@@ -3360,6 +3362,7 @@ static struct extern_resource *sm4_get_extern_resources(struct hlsl_ctx *ctx, un
extern_resources[*count].regset = HLSL_REGSET_NUMERIC;
extern_resources[*count].id = buffer->reg.id;
extern_resources[*count].index = buffer->reg.index;
extern_resources[*count].bind_count = 1;
++*count;
@@ -3456,7 +3459,7 @@ static void write_sm4_rdef(struct hlsl_ctx *ctx, struct dxbc_writer *dxbc)
put_u32(&buffer, 0);
put_u32(&buffer, 0);
}
put_u32(&buffer, resource->id);
put_u32(&buffer, resource->index);
put_u32(&buffer, resource->bind_count);
put_u32(&buffer, flags);
}
@@ -3754,30 +3757,57 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct vkd3d_shader_re
{
reg->type = VKD3DSPR_RESOURCE;
reg->dimension = VSIR_DIMENSION_VEC4;
reg->idx[0].offset = var->regs[HLSL_REGSET_TEXTURES].id;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
if (hlsl_version_ge(ctx, 5, 1))
{
reg->idx[0].offset = var->regs[HLSL_REGSET_TEXTURES].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_TEXTURES].index; /* FIXME: array index */
reg->idx_count = 2;
}
else
{
reg->idx[0].offset = var->regs[HLSL_REGSET_TEXTURES].index;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 1;
}
assert(regset == HLSL_REGSET_TEXTURES);
reg->idx_count = 1;
*writemask = VKD3DSP_WRITEMASK_ALL;
}
else if (regset == HLSL_REGSET_UAVS)
{
reg->type = VKD3DSPR_UAV;
reg->dimension = VSIR_DIMENSION_VEC4;
reg->idx[0].offset = var->regs[HLSL_REGSET_UAVS].id;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
if (hlsl_version_ge(ctx, 5, 1))
{
reg->idx[0].offset = var->regs[HLSL_REGSET_UAVS].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_UAVS].index; /* FIXME: array index */
reg->idx_count = 2;
}
else
{
reg->idx[0].offset = var->regs[HLSL_REGSET_UAVS].index;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 1;
}
assert(regset == HLSL_REGSET_UAVS);
reg->idx_count = 1;
*writemask = VKD3DSP_WRITEMASK_ALL;
}
else if (regset == HLSL_REGSET_SAMPLERS)
{
reg->type = VKD3DSPR_SAMPLER;
reg->dimension = VSIR_DIMENSION_NONE;
reg->idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].id;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
if (hlsl_version_ge(ctx, 5, 1))
{
reg->idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].id;
reg->idx[1].offset = var->regs[HLSL_REGSET_SAMPLERS].index; /* FIXME: array index */
reg->idx_count = 2;
}
else
{
reg->idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].index;
reg->idx[0].offset += hlsl_offset_from_deref_safe(ctx, deref);
reg->idx_count = 1;
}
assert(regset == HLSL_REGSET_SAMPLERS);
reg->idx_count = 1;
*writemask = VKD3DSP_WRITEMASK_ALL;
}
else
@@ -3787,9 +3817,19 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct vkd3d_shader_re
assert(data_type->class <= HLSL_CLASS_VECTOR);
reg->type = VKD3DSPR_CONSTBUFFER;
reg->dimension = VSIR_DIMENSION_VEC4;
reg->idx[0].offset = var->buffer->reg.id;
reg->idx[1].offset = offset / 4;
reg->idx_count = 2;
if (hlsl_version_ge(ctx, 5, 1))
{
reg->idx[0].offset = var->buffer->reg.id;
reg->idx[1].offset = var->buffer->reg.index; /* FIXME: array index */
reg->idx[2].offset = offset / 4;
reg->idx_count = 3;
}
else
{
reg->idx[0].offset = var->buffer->reg.index;
reg->idx[1].offset = offset / 4;
reg->idx_count = 2;
}
*writemask = ((1u << data_type->dimx) - 1) << (offset & 3);
}
}
@@ -4173,18 +4213,35 @@ static bool encode_texel_offset_as_aoffimmi(struct sm4_instruction *instr,
static void write_sm4_dcl_constant_buffer(const struct tpf_writer *tpf, const struct hlsl_buffer *cbuffer)
{
const struct sm4_instruction instr =
size_t size = (cbuffer->used_size + 3) / 4;
struct sm4_instruction instr =
{
.opcode = VKD3D_SM4_OP_DCL_CONSTANT_BUFFER,
.srcs[0].reg.dimension = VSIR_DIMENSION_VEC4,
.srcs[0].reg.type = VKD3DSPR_CONSTBUFFER,
.srcs[0].reg.idx[0].offset = cbuffer->reg.id,
.srcs[0].reg.idx[1].offset = (cbuffer->used_size + 3) / 4,
.srcs[0].reg.idx_count = 2,
.srcs[0].swizzle = VKD3D_SHADER_NO_SWIZZLE,
.src_count = 1,
};
if (hlsl_version_ge(tpf->ctx, 5, 1))
{
instr.srcs[0].reg.idx[0].offset = cbuffer->reg.id;
instr.srcs[0].reg.idx[1].offset = cbuffer->reg.index;
instr.srcs[0].reg.idx[2].offset = cbuffer->reg.index; /* FIXME: array end */
instr.srcs[0].reg.idx_count = 3;
instr.idx[0] = size;
instr.idx_count = 1;
}
else
{
instr.srcs[0].reg.idx[0].offset = cbuffer->reg.index;
instr.srcs[0].reg.idx[1].offset = size;
instr.srcs[0].reg.idx_count = 2;
}
write_sm4_instruction(tpf, &instr);
}
@@ -4197,7 +4254,6 @@ static void write_sm4_dcl_samplers(const struct tpf_writer *tpf, const struct ex
.opcode = VKD3D_SM4_OP_DCL_SAMPLER,
.dsts[0].reg.type = VKD3DSPR_SAMPLER,
.dsts[0].reg.idx_count = 1,
.dst_count = 1,
};
@@ -4213,7 +4269,19 @@ static void write_sm4_dcl_samplers(const struct tpf_writer *tpf, const struct ex
if (resource->var && !resource->var->objects_usage[HLSL_REGSET_SAMPLERS][i].used)
continue;
instr.dsts[0].reg.idx[0].offset = resource->id + i;
if (hlsl_version_ge(tpf->ctx, 5, 1))
{
assert(!i);
instr.dsts[0].reg.idx[0].offset = resource->id;
instr.dsts[0].reg.idx[1].offset = resource->index;
instr.dsts[0].reg.idx[2].offset = resource->index; /* FIXME: array end */
instr.dsts[0].reg.idx_count = 3;
}
else
{
instr.dsts[0].reg.idx[0].offset = resource->index + i;
instr.dsts[0].reg.idx_count = 1;
}
write_sm4_instruction(tpf, &instr);
}
}
@@ -4246,6 +4314,20 @@ static void write_sm4_dcl_textures(const struct tpf_writer *tpf, const struct ex
.idx_count = 1,
};
if (hlsl_version_ge(tpf->ctx, 5, 1))
{
assert(!i);
instr.dsts[0].reg.idx[0].offset = resource->id;
instr.dsts[0].reg.idx[1].offset = resource->index;
instr.dsts[0].reg.idx[2].offset = resource->index; /* FIXME: array end */
instr.dsts[0].reg.idx_count = 3;
}
else
{
instr.dsts[0].reg.idx[0].offset = resource->index + i;
instr.dsts[0].reg.idx_count = 1;
}
if (uav)
{
switch (resource->data_type->sampler_dim)