mirror of
https://gitlab.winehq.org/wine/vkd3d.git
synced 2024-11-21 16:46:41 -08:00
vkd3d-shader/hlsl: Save hlsl_ir_constants in the vsir_program for SM1.
This commit is contained in:
parent
a61846c28a
commit
23e3ec84f7
Notes:
Henri Verbeet
2024-09-04 18:48:04 +02:00
Approved-by: Elizabeth Figura (@zfigura) Approved-by: Henri Verbeet (@hverbeet) Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/941
@ -1468,6 +1468,7 @@ bool hlsl_sm1_usage_from_semantic(const char *semantic_name,
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struct d3dbc_compiler
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struct d3dbc_compiler
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{
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{
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const struct vkd3d_sm1_opcode_info *opcode_table;
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struct vsir_program *program;
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struct vsir_program *program;
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struct vkd3d_bytecode_buffer buffer;
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struct vkd3d_bytecode_buffer buffer;
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struct vkd3d_shader_message_context *message_context;
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struct vkd3d_shader_message_context *message_context;
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@ -2170,6 +2171,75 @@ static void d3dbc_write_cast(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
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}
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}
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}
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}
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static const struct vkd3d_sm1_opcode_info *shader_sm1_get_opcode_info_from_vsir(
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struct d3dbc_compiler *d3dbc, enum vkd3d_shader_opcode vkd3d_opcode)
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{
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const struct vkd3d_shader_version *version = &d3dbc->program->shader_version;
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const struct vkd3d_sm1_opcode_info *info;
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unsigned int i = 0;
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for (;;)
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{
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info = &d3dbc->opcode_table[i++];
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if (info->vkd3d_opcode == VKD3DSIH_INVALID)
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return NULL;
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if (vkd3d_opcode == info->vkd3d_opcode
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&& vkd3d_shader_ver_ge(version, info->min_version.major, info->min_version.minor)
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&& (vkd3d_shader_ver_le(version, info->max_version.major, info->max_version.minor)
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|| !info->max_version.major))
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return info;
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}
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}
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static uint32_t swizzle_from_vsir(uint32_t swizzle)
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{
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uint32_t x = vsir_swizzle_get_component(swizzle, 0);
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uint32_t y = vsir_swizzle_get_component(swizzle, 1);
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uint32_t z = vsir_swizzle_get_component(swizzle, 2);
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uint32_t w = vsir_swizzle_get_component(swizzle, 3);
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if (x & ~0x3u || y & ~0x3u || z & ~0x3u || w & ~0x3u)
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ERR("Unexpected vsir swizzle: 0x%08x.\n", swizzle);
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return ((x & 0x3u) << VKD3D_SM1_SWIZZLE_COMPONENT_SHIFT(0))
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| ((y & 0x3) << VKD3D_SM1_SWIZZLE_COMPONENT_SHIFT(1))
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| ((z & 0x3) << VKD3D_SM1_SWIZZLE_COMPONENT_SHIFT(2))
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| ((w & 0x3) << VKD3D_SM1_SWIZZLE_COMPONENT_SHIFT(3));
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}
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static void sm1_src_reg_from_vsir(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_src_param *param,
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struct sm1_src_register *src, const struct vkd3d_shader_location *loc)
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{
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src->mod = (uint32_t)param->modifiers << VKD3D_SM1_SRC_MODIFIER_SHIFT;
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src->reg = param->reg.idx[0].offset;
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src->type = param->reg.type;
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src->swizzle = swizzle_from_vsir(param->swizzle);
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if (param->reg.idx[0].rel_addr)
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{
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vkd3d_shader_error(d3dbc->message_context, loc, VKD3D_SHADER_ERROR_D3DBC_NOT_IMPLEMENTED,
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"Unhandled relative addressing on source register.");
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d3dbc->failed = true;
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}
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}
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static void sm1_dst_reg_from_vsir(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_dst_param *param,
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struct sm1_dst_register *dst, const struct vkd3d_shader_location *loc)
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{
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dst->mod = (uint32_t)param->modifiers << VKD3D_SM1_DST_MODIFIER_SHIFT;
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dst->reg = param->reg.idx[0].offset;
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dst->type = param->reg.type;
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dst->writemask = param->write_mask;
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if (param->reg.idx[0].rel_addr)
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{
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vkd3d_shader_error(d3dbc->message_context, loc, VKD3D_SHADER_ERROR_D3DBC_NOT_IMPLEMENTED,
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"Unhandled relative addressing on destination register.");
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d3dbc->failed = true;
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}
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}
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static void d3dbc_write_vsir_def(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_instruction *ins)
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static void d3dbc_write_vsir_def(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_instruction *ins)
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{
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{
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const struct vkd3d_shader_version *version = &d3dbc->program->shader_version;
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const struct vkd3d_shader_version *version = &d3dbc->program->shader_version;
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@ -2258,6 +2328,43 @@ static void d3dbc_write_vsir_dcl(struct d3dbc_compiler *d3dbc, const struct vkd3
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}
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}
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}
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}
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static void d3dbc_write_vsir_simple_instruction(struct d3dbc_compiler *d3dbc,
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const struct vkd3d_shader_instruction *ins)
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{
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const struct vkd3d_sm1_opcode_info *info;
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struct sm1_instruction instr = {0};
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info = shader_sm1_get_opcode_info_from_vsir(d3dbc, ins->opcode);
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if (ins->dst_count != info->dst_count)
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{
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vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_COUNT,
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"Invalid destination count %u for vsir instruction %#x (expected %u).",
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ins->dst_count, ins->opcode, info->dst_count);
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d3dbc->failed = true;
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return;
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}
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if (ins->src_count != info->src_count)
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{
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vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_COUNT,
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"Invalid source count %u for vsir instruction %#x (expected %u).",
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ins->src_count, ins->opcode, info->src_count);
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d3dbc->failed = true;
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return;
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}
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instr.opcode = (D3DSHADER_INSTRUCTION_OPCODE_TYPE)info->sm1_opcode;
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instr.has_dst = info->dst_count;
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instr.src_count = info->src_count;
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if (instr.has_dst)
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sm1_dst_reg_from_vsir(d3dbc, &ins->dst[0], &instr.dst, &ins->location);
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for (unsigned int i = 0; i < instr.src_count; ++i)
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sm1_src_reg_from_vsir(d3dbc, &ins->src[i], &instr.srcs[i], &ins->location);
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d3dbc_write_instruction(d3dbc, &instr);
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}
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static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_instruction *ins)
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static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const struct vkd3d_shader_instruction *ins)
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{
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{
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switch (ins->opcode)
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switch (ins->opcode)
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@ -2270,6 +2377,10 @@ static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const str
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d3dbc_write_vsir_dcl(d3dbc, ins);
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d3dbc_write_vsir_dcl(d3dbc, ins);
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break;
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break;
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case VKD3DSIH_MOV:
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d3dbc_write_vsir_simple_instruction(d3dbc, ins);
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break;
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default:
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default:
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vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_OPCODE,
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vkd3d_shader_error(d3dbc->message_context, &ins->location, VKD3D_SHADER_ERROR_D3DBC_INVALID_OPCODE,
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"vsir instruction with opcode %#x.", ins->opcode);
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"vsir instruction with opcode %#x.", ins->opcode);
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@ -2343,30 +2454,6 @@ static void d3dbc_write_semantic_dcls(struct d3dbc_compiler *d3dbc)
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}
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}
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}
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}
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static void d3dbc_write_constant(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_node *instr)
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{
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const struct hlsl_ir_constant *constant = hlsl_ir_constant(instr);
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struct sm1_instruction sm1_instr =
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{
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.opcode = D3DSIO_MOV,
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.dst.type = VKD3DSPR_TEMP,
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.dst.reg = instr->reg.id,
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.dst.writemask = instr->reg.writemask,
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.has_dst = 1,
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.srcs[0].type = VKD3DSPR_CONST,
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.srcs[0].reg = constant->reg.id,
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.srcs[0].swizzle = hlsl_swizzle_from_writemask(constant->reg.writemask),
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.src_count = 1,
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};
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VKD3D_ASSERT(instr->reg.allocated);
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VKD3D_ASSERT(constant->reg.allocated);
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sm1_map_src_swizzle(&sm1_instr.srcs[0], sm1_instr.dst.writemask);
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d3dbc_write_instruction(d3dbc, &sm1_instr);
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}
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static void d3dbc_write_per_component_unary_op(struct d3dbc_compiler *d3dbc,
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static void d3dbc_write_per_component_unary_op(struct d3dbc_compiler *d3dbc,
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const struct hlsl_ir_node *instr, D3DSHADER_INSTRUCTION_OPCODE_TYPE opcode)
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const struct hlsl_ir_node *instr, D3DSHADER_INSTRUCTION_OPCODE_TYPE opcode)
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{
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{
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@ -2847,10 +2934,6 @@ static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_bl
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case HLSL_IR_CALL:
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case HLSL_IR_CALL:
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vkd3d_unreachable();
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vkd3d_unreachable();
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case HLSL_IR_CONSTANT:
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d3dbc_write_constant(d3dbc, instr);
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break;
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case HLSL_IR_EXPR:
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case HLSL_IR_EXPR:
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d3dbc_write_expr(d3dbc, instr);
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d3dbc_write_expr(d3dbc, instr);
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break;
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break;
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@ -2911,6 +2994,21 @@ int d3dbc_compile(struct vsir_program *program, uint64_t config_flags,
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d3dbc.ctx = ctx;
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d3dbc.ctx = ctx;
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d3dbc.program = program;
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d3dbc.program = program;
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d3dbc.message_context = message_context;
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d3dbc.message_context = message_context;
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switch (version->type)
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{
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case VKD3D_SHADER_TYPE_VERTEX:
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d3dbc.opcode_table = vs_opcode_table;
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break;
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case VKD3D_SHADER_TYPE_PIXEL:
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d3dbc.opcode_table = ps_opcode_table;
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break;
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default:
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vkd3d_shader_error(message_context, NULL, VKD3D_SHADER_ERROR_D3DBC_INVALID_PROFILE,
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"Invalid shader type %u.", version->type);
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return VKD3D_ERROR_INVALID_SHADER;
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}
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put_u32(buffer, sm1_version(version->type, version->major, version->minor));
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put_u32(buffer, sm1_version(version->type, version->major, version->minor));
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@ -70,6 +70,14 @@ static inline unsigned int hlsl_swizzle_get_component(uint32_t swizzle, unsigned
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return (swizzle >> HLSL_SWIZZLE_SHIFT(idx)) & HLSL_SWIZZLE_MASK;
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return (swizzle >> HLSL_SWIZZLE_SHIFT(idx)) & HLSL_SWIZZLE_MASK;
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}
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}
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static inline uint32_t vsir_swizzle_from_hlsl(uint32_t swizzle)
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{
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return vkd3d_shader_create_swizzle(hlsl_swizzle_get_component(swizzle, 0),
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hlsl_swizzle_get_component(swizzle, 1),
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hlsl_swizzle_get_component(swizzle, 2),
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hlsl_swizzle_get_component(swizzle, 3));
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}
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enum hlsl_type_class
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enum hlsl_type_class
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{
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{
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HLSL_CLASS_SCALAR,
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HLSL_CLASS_SCALAR,
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@ -6014,6 +6014,16 @@ static void sm1_generate_vsir_signature(struct hlsl_ctx *ctx, struct vsir_progra
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}
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}
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}
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}
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static uint32_t sm1_generate_vsir_get_src_swizzle(uint32_t src_writemask, uint32_t dst_writemask)
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{
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uint32_t swizzle;
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swizzle = hlsl_swizzle_from_writemask(src_writemask);
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swizzle = hlsl_map_swizzle(swizzle, dst_writemask);
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swizzle = vsir_swizzle_from_hlsl(swizzle);
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return swizzle;
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}
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static void sm1_generate_vsir_constant_defs(struct hlsl_ctx *ctx, struct vsir_program *program,
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static void sm1_generate_vsir_constant_defs(struct hlsl_ctx *ctx, struct vsir_program *program,
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struct hlsl_block *block)
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struct hlsl_block *block)
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{
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{
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@ -6157,6 +6167,70 @@ static void sm1_generate_vsir_sampler_dcls(struct hlsl_ctx *ctx,
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}
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}
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}
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}
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static void sm1_generate_vsir_instr_constant(struct hlsl_ctx *ctx,
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struct vsir_program *program, struct hlsl_ir_constant *constant)
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{
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struct vkd3d_shader_instruction_array *instructions = &program->instructions;
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struct hlsl_ir_node *instr = &constant->node;
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struct vkd3d_shader_dst_param *dst_param;
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struct vkd3d_shader_src_param *src_param;
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struct vkd3d_shader_instruction *ins;
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struct hlsl_ir_node *vsir_instr;
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VKD3D_ASSERT(instr->reg.allocated);
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VKD3D_ASSERT(constant->reg.allocated);
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if (!shader_instruction_array_reserve(instructions, instructions->count + 1))
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{
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ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
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return;
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}
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ins = &instructions->elements[instructions->count];
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if (!vsir_instruction_init_with_params(program, ins, &instr->loc, VKD3DSIH_MOV, 1, 1))
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{
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ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
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return;
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}
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++instructions->count;
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src_param = &ins->src[0];
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vsir_register_init(&src_param->reg, VKD3DSPR_CONST, VKD3D_DATA_FLOAT, 1);
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src_param->reg.idx[0].offset = constant->reg.id;
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src_param->swizzle = sm1_generate_vsir_get_src_swizzle(constant->reg.writemask, instr->reg.writemask);
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dst_param = &ins->dst[0];
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vsir_register_init(&dst_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
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dst_param->reg.idx[0].offset = instr->reg.id;
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dst_param->write_mask = instr->reg.writemask;
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if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, instructions->count - 1,
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instr->data_type, &instr->reg, &instr->loc)))
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{
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ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
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return;
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}
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list_add_before(&instr->entry, &vsir_instr->entry);
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hlsl_replace_node(instr, vsir_instr);
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}
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static bool sm1_generate_vsir_instr(struct hlsl_ctx *ctx, struct hlsl_ir_node *instr, void *context)
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{
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struct vsir_program *program = context;
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switch (instr->type)
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{
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case HLSL_IR_CONSTANT:
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|
sm1_generate_vsir_instr_constant(ctx, program, hlsl_ir_constant(instr));
|
||||||
|
return true;
|
||||||
|
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
/* OBJECTIVE: Translate all the information from ctx and entry_func to the
|
/* OBJECTIVE: Translate all the information from ctx and entry_func to the
|
||||||
* vsir_program and ctab blob, so they can be used as input to d3dbc_compile()
|
* vsir_program and ctab blob, so they can be used as input to d3dbc_compile()
|
||||||
* without relying on ctx and entry_func. */
|
* without relying on ctx and entry_func. */
|
||||||
@ -6192,6 +6266,8 @@ static void sm1_generate_vsir(struct hlsl_ctx *ctx, struct hlsl_ir_function_decl
|
|||||||
sm1_generate_vsir_constant_defs(ctx, program, &block);
|
sm1_generate_vsir_constant_defs(ctx, program, &block);
|
||||||
sm1_generate_vsir_sampler_dcls(ctx, program, &block);
|
sm1_generate_vsir_sampler_dcls(ctx, program, &block);
|
||||||
list_move_head(&entry_func->body.instrs, &block.instrs);
|
list_move_head(&entry_func->body.instrs, &block.instrs);
|
||||||
|
|
||||||
|
hlsl_transform_ir(ctx, sm1_generate_vsir_instr, &entry_func->body, program);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct hlsl_ir_jump *loop_unrolling_find_jump(struct hlsl_block *block, struct hlsl_ir_node *stop_point,
|
static struct hlsl_ir_jump *loop_unrolling_find_jump(struct hlsl_block *block, struct hlsl_ir_node *stop_point,
|
||||||
|
@ -170,6 +170,9 @@ enum vkd3d_shader_error
|
|||||||
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_INDEX = 7005,
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_INDEX = 7005,
|
||||||
VKD3D_SHADER_ERROR_D3DBC_UNDECLARED_SEMANTIC = 7006,
|
VKD3D_SHADER_ERROR_D3DBC_UNDECLARED_SEMANTIC = 7006,
|
||||||
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_TYPE = 7007,
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_TYPE = 7007,
|
||||||
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_REGISTER_COUNT = 7008,
|
||||||
|
VKD3D_SHADER_ERROR_D3DBC_NOT_IMPLEMENTED = 7009,
|
||||||
|
VKD3D_SHADER_ERROR_D3DBC_INVALID_PROFILE = 7010,
|
||||||
|
|
||||||
VKD3D_SHADER_WARNING_D3DBC_IGNORED_INSTRUCTION_FLAGS= 7300,
|
VKD3D_SHADER_WARNING_D3DBC_IGNORED_INSTRUCTION_FLAGS= 7300,
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user