vkd3d: Support signalling a fence once all outstanding work is submitted to Vulkan.

When the client acquires the Vulkan queue it has to ensure that
it is not submitting work before other work it depends on already
submitted through the Direct3D 12 API but currently in the internal
vkd3d queue. Currently we suggest to enqueue signalling a fence and
than wait for it before acquiring the Vulkan queue, which is
correct but excessive: it will wait not just for the work currently
in the queue to be submitted, but for it to be executed too,
introducing useless dependencies.

By adding a way to enqueue signalling a fence on the CPU side we
allow the client to wait for the currently outstanding work to
be submitted to Vulkan, but nothing more.
This commit is contained in:
Giovanni Mascellani
2025-01-16 12:53:01 +01:00
committed by Henri Verbeet
parent bdb8291f6c
commit 22d0841412
Notes: Henri Verbeet 2025-01-21 14:13:31 +01:00
Approved-by: Henri Verbeet (@hverbeet)
Approved-by: Giovanni Mascellani (@giomasce)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1343
5 changed files with 139 additions and 3 deletions

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@@ -6455,6 +6455,7 @@ static void d3d12_command_queue_destroy_op(struct vkd3d_cs_op_data *op)
break;
case VKD3D_CS_OP_SIGNAL:
case VKD3D_CS_OP_SIGNAL_ON_CPU:
d3d12_fence_decref(op->u.signal.fence);
break;
@@ -7445,6 +7446,7 @@ static HRESULT d3d12_command_queue_flush_ops_locked(struct d3d12_command_queue *
struct vkd3d_cs_op_data *op;
struct d3d12_fence *fence;
unsigned int i;
HRESULT hr;
queue->is_flushing = true;
@@ -7478,6 +7480,11 @@ static HRESULT d3d12_command_queue_flush_ops_locked(struct d3d12_command_queue *
d3d12_command_queue_signal(queue, op->u.signal.fence, op->u.signal.value);
break;
case VKD3D_CS_OP_SIGNAL_ON_CPU:
if (FAILED(hr = d3d12_fence_Signal(&op->u.signal.fence->ID3D12Fence1_iface, op->u.signal.value)))
ERR("Failed to signal fence %p, hr %s.\n", op->u.signal.fence, debugstr_hresult(hr));
break;
case VKD3D_CS_OP_EXECUTE:
d3d12_command_queue_execute(queue, op->u.execute.buffers, op->u.execute.buffer_count);
break;
@@ -7620,6 +7627,36 @@ void vkd3d_release_vk_queue(ID3D12CommandQueue *queue)
return vkd3d_queue_release(d3d12_queue->vkd3d_queue);
}
HRESULT vkd3d_queue_signal_on_cpu(ID3D12CommandQueue *iface, ID3D12Fence *fence_iface, uint64_t value)
{
struct d3d12_command_queue *command_queue = impl_from_ID3D12CommandQueue(iface);
struct d3d12_fence *fence = unsafe_impl_from_ID3D12Fence(fence_iface);
struct vkd3d_cs_op_data *op;
HRESULT hr = S_OK;
TRACE("iface %p, fence %p, value %#"PRIx64".\n", iface, fence_iface, value);
vkd3d_mutex_lock(&command_queue->op_mutex);
if (!(op = d3d12_command_queue_op_array_require_space(&command_queue->op_queue)))
{
ERR("Failed to add op.\n");
hr = E_OUTOFMEMORY;
goto done;
}
op->opcode = VKD3D_CS_OP_SIGNAL_ON_CPU;
op->u.signal.fence = fence;
op->u.signal.value = value;
d3d12_fence_incref(fence);
d3d12_command_queue_submit_locked(command_queue);
done:
vkd3d_mutex_unlock(&command_queue->op_mutex);
return hr;
}
/* ID3D12CommandSignature */
static inline struct d3d12_command_signature *impl_from_ID3D12CommandSignature(ID3D12CommandSignature *iface)
{

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@@ -17,6 +17,7 @@ global:
vkd3d_instance_from_device;
vkd3d_instance_get_vk_instance;
vkd3d_instance_incref;
vkd3d_queue_signal_on_cpu;
vkd3d_release_vk_queue;
vkd3d_resource_decref;
vkd3d_resource_incref;

View File

@@ -1364,6 +1364,7 @@ enum vkd3d_cs_op
{
VKD3D_CS_OP_WAIT,
VKD3D_CS_OP_SIGNAL,
VKD3D_CS_OP_SIGNAL_ON_CPU,
VKD3D_CS_OP_EXECUTE,
VKD3D_CS_OP_UPDATE_MAPPINGS,
VKD3D_CS_OP_COPY_MAPPINGS,