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vkd3d-shader/hlsl: Save hlsl_ir_resource_load in the vsir_program for SM1.

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Francisco Casas 2024-06-03 22:23:53 -04:00 committed by Henri Verbeet
parent 961c4f8b23
commit 08fb683784
Notes: Henri Verbeet 2024-09-12 18:57:08 +02:00 
Approved-by: Elizabeth Figura (@zfigura)
Approved-by: Henri Verbeet (@hverbeet)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/1062
2 changed files with 125 additions and 86 deletions
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77
libs/vkd3d-shader/d3dbc.c
View File

@ -2203,6 +2203,8 @@ static void d3dbc_write_vsir_instruction(struct d3dbc_compiler *d3dbc, const str
case VKD3DSIH_MUL: case VKD3DSIH_MUL:
case VKD3DSIH_SINCOS: case VKD3DSIH_SINCOS:
case VKD3DSIH_SLT: case VKD3DSIH_SLT:
case VKD3DSIH_TEX:
case VKD3DSIH_TEXLDD:
d3dbc_write_vsir_simple_instruction(d3dbc, ins); d3dbc_write_vsir_simple_instruction(d3dbc, ins);
break; break;
@ -2367,77 +2369,6 @@ static void d3dbc_write_jump(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_
} }
} }
static void d3dbc_write_resource_load(struct d3dbc_compiler *d3dbc, const struct hlsl_ir_node *instr)
{
const struct hlsl_ir_resource_load *load = hlsl_ir_resource_load(instr);
struct hlsl_ir_node *coords = load->coords.node;
struct hlsl_ir_node *ddx = load->ddx.node;
struct hlsl_ir_node *ddy = load->ddy.node;
unsigned int sampler_offset, reg_id;
struct hlsl_ctx *ctx = d3dbc->ctx;
struct sm1_instruction sm1_instr;
sampler_offset = hlsl_offset_from_deref_safe(ctx, &load->resource);
reg_id = load->resource.var->regs[HLSL_REGSET_SAMPLERS].index + sampler_offset;
sm1_instr = (struct sm1_instruction)
{
.dst.type = VKD3DSPR_TEMP,
.dst.reg = instr->reg.id,
.dst.writemask = instr->reg.writemask,
.has_dst = 1,
.srcs[0].type = VKD3DSPR_TEMP,
.srcs[0].reg = coords->reg.id,
.srcs[0].swizzle = hlsl_swizzle_from_writemask(coords->reg.writemask),
.srcs[1].type = VKD3DSPR_COMBINED_SAMPLER,
.srcs[1].reg = reg_id,
.srcs[1].swizzle = hlsl_swizzle_from_writemask(VKD3DSP_WRITEMASK_ALL),
.src_count = 2,
};
switch (load->load_type)
{
case HLSL_RESOURCE_SAMPLE:
sm1_instr.opcode = VKD3D_SM1_OP_TEX;
break;
case HLSL_RESOURCE_SAMPLE_PROJ:
sm1_instr.opcode = VKD3D_SM1_OP_TEX;
sm1_instr.opcode |= VKD3DSI_TEXLD_PROJECT << VKD3D_SM1_INSTRUCTION_FLAGS_SHIFT;
break;
case HLSL_RESOURCE_SAMPLE_LOD_BIAS:
sm1_instr.opcode = VKD3D_SM1_OP_TEX;
sm1_instr.opcode |= VKD3DSI_TEXLD_BIAS << VKD3D_SM1_INSTRUCTION_FLAGS_SHIFT;
break;
case HLSL_RESOURCE_SAMPLE_GRAD:
sm1_instr.opcode = VKD3D_SM1_OP_TEXLDD;
sm1_instr.srcs[2].type = VKD3DSPR_TEMP;
sm1_instr.srcs[2].reg = ddx->reg.id;
sm1_instr.srcs[2].swizzle = hlsl_swizzle_from_writemask(ddx->reg.writemask);
sm1_instr.srcs[3].type = VKD3DSPR_TEMP;
sm1_instr.srcs[3].reg = ddy->reg.id;
sm1_instr.srcs[3].swizzle = hlsl_swizzle_from_writemask(ddy->reg.writemask);
sm1_instr.src_count += 2;
break;
default:
hlsl_fixme(ctx, &instr->loc, "Resource load type %u.", load->load_type);
return;
}
VKD3D_ASSERT(instr->reg.allocated);
d3dbc_write_instruction(d3dbc, &sm1_instr);
}
static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_block *block) static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_block *block)
{ {
struct vkd3d_shader_instruction *vsir_instr; struct vkd3d_shader_instruction *vsir_instr;
@ -2472,10 +2403,6 @@ static void d3dbc_write_block(struct d3dbc_compiler *d3dbc, const struct hlsl_bl
d3dbc_write_jump(d3dbc, instr); d3dbc_write_jump(d3dbc, instr);
break; break;
case HLSL_IR_RESOURCE_LOAD:
d3dbc_write_resource_load(d3dbc, instr);
break;
case HLSL_IR_VSIR_INSTRUCTION_REF: case HLSL_IR_VSIR_INSTRUCTION_REF:
vsir_instr_idx = hlsl_ir_vsir_instruction_ref(instr)->vsir_instr_idx; vsir_instr_idx = hlsl_ir_vsir_instruction_ref(instr)->vsir_instr_idx;
vsir_instr = &d3dbc->program->instructions.elements[vsir_instr_idx]; vsir_instr = &d3dbc->program->instructions.elements[vsir_instr_idx];

134
libs/vkd3d-shader/hlsl_codegen.c
View File

@ -6957,29 +6957,52 @@ static void sm1_generate_vsir_init_src_param_from_deref(struct hlsl_ctx *ctx,
unsigned int writemask; unsigned int writemask;
struct hlsl_reg reg; struct hlsl_reg reg;
reg = hlsl_reg_from_deref(ctx, deref); if (hlsl_type_is_resource(deref->var->data_type))
register_index = reg.id; {
writemask = reg.writemask; unsigned int sampler_offset;
if (deref->var->is_uniform) type = VKD3DSPR_COMBINED_SAMPLER;
sampler_offset = hlsl_offset_from_deref_safe(ctx, deref);
register_index = deref->var->regs[HLSL_REGSET_SAMPLERS].index + sampler_offset;
writemask = VKD3DSP_WRITEMASK_ALL;
}
else if (deref->var->is_uniform)
{ {
VKD3D_ASSERT(reg.allocated);
type = VKD3DSPR_CONST; type = VKD3DSPR_CONST;
reg = hlsl_reg_from_deref(ctx, deref);
register_index = reg.id;
writemask = reg.writemask;
VKD3D_ASSERT(reg.allocated);
} }
else if (deref->var->is_input_semantic) else if (deref->var->is_input_semantic)
{ {
version.major = ctx->profile->major_version; version.major = ctx->profile->major_version;
version.minor = ctx->profile->minor_version; version.minor = ctx->profile->minor_version;
version.type = ctx->profile->type; version.type = ctx->profile->type;
if (!hlsl_sm1_register_from_semantic(&version, deref->var->semantic.name, if (hlsl_sm1_register_from_semantic(&version, deref->var->semantic.name,
deref->var->semantic.index, false, &type, &register_index)) deref->var->semantic.index, false, &type, &register_index))
{ {
VKD3D_ASSERT(reg.allocated); writemask = (1 << deref->var->data_type->dimx) - 1;
type = VKD3DSPR_INPUT;
register_index = reg.id;
} }
else else
writemask = (1 << deref->var->data_type->dimx) - 1; {
type = VKD3DSPR_INPUT;
reg = hlsl_reg_from_deref(ctx, deref);
register_index = reg.id;
writemask = reg.writemask;
VKD3D_ASSERT(reg.allocated);
}
}
else
{
type = VKD3DSPR_TEMP;
reg = hlsl_reg_from_deref(ctx, deref);
register_index = reg.id;
writemask = reg.writemask;
} }
vsir_register_init(&src_param->reg, type, VKD3D_DATA_FLOAT, 1); vsir_register_init(&src_param->reg, type, VKD3D_DATA_FLOAT, 1);
@ -7023,6 +7046,91 @@ static void sm1_generate_vsir_instr_load(struct hlsl_ctx *ctx, struct vsir_progr
hlsl_replace_node(instr, vsir_instr); hlsl_replace_node(instr, vsir_instr);
} }
static void sm1_generate_vsir_instr_resource_load(struct hlsl_ctx *ctx,
struct vsir_program *program, struct hlsl_ir_resource_load *load)
{
struct vkd3d_shader_instruction_array *instructions = &program->instructions;
struct hlsl_ir_node *coords = load->coords.node;
struct hlsl_ir_node *ddx = load->ddx.node;
struct hlsl_ir_node *ddy = load->ddy.node;
struct hlsl_ir_node *instr = &load->node;
struct vkd3d_shader_dst_param *dst_param;
struct vkd3d_shader_src_param *src_param;
struct vkd3d_shader_instruction *ins;
struct hlsl_ir_node *vsir_instr;
enum vkd3d_shader_opcode opcode;
unsigned int src_count = 2;
uint32_t flags = 0;
VKD3D_ASSERT(instr->reg.allocated);
switch (load->load_type)
{
case HLSL_RESOURCE_SAMPLE:
opcode = VKD3DSIH_TEX;
break;
case HLSL_RESOURCE_SAMPLE_PROJ:
opcode = VKD3DSIH_TEX;
flags |= VKD3DSI_TEXLD_PROJECT;
break;
case HLSL_RESOURCE_SAMPLE_LOD_BIAS:
opcode = VKD3DSIH_TEX;
flags |= VKD3DSI_TEXLD_BIAS;
break;
case HLSL_RESOURCE_SAMPLE_GRAD:
opcode = VKD3DSIH_TEXLDD;
src_count += 2;
break;
default:
hlsl_fixme(ctx, &instr->loc, "Resource load type %u.", load->load_type);
return;
}
if (!(ins = generate_vsir_add_program_instruction(ctx, program, &instr->loc, opcode, 1, src_count)))
return;
ins->flags = flags;
dst_param = &ins->dst[0];
vsir_register_init(&dst_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
dst_param->reg.idx[0].offset = instr->reg.id;
dst_param->write_mask = instr->reg.writemask;
src_param = &ins->src[0];
vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = coords->reg.id;
src_param->swizzle = sm1_generate_vsir_get_src_swizzle(coords->reg.writemask, VKD3DSP_WRITEMASK_ALL);
sm1_generate_vsir_init_src_param_from_deref(ctx, &ins->src[1], &load->resource,
VKD3DSP_WRITEMASK_ALL, &ins->location);
if (load->load_type == HLSL_RESOURCE_SAMPLE_GRAD)
{
src_param = &ins->src[2];
vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = ddx->reg.id;
src_param->swizzle = sm1_generate_vsir_get_src_swizzle(ddx->reg.writemask, VKD3DSP_WRITEMASK_ALL);
src_param = &ins->src[3];
vsir_register_init(&src_param->reg, VKD3DSPR_TEMP, VKD3D_DATA_FLOAT, 1);
src_param->reg.idx[0].offset = ddy->reg.id;
src_param->swizzle = sm1_generate_vsir_get_src_swizzle(ddy->reg.writemask, VKD3DSP_WRITEMASK_ALL);
}
if (!(vsir_instr = hlsl_new_vsir_instruction_ref(ctx, instructions->count - 1, instr->data_type,
&instr->reg, &instr->loc)))
{
ctx->result = VKD3D_ERROR_OUT_OF_MEMORY;
return;
}
list_add_before(&instr->entry, &vsir_instr->entry);
hlsl_replace_node(instr, vsir_instr);
}
static void sm1_generate_vsir_instr_swizzle(struct hlsl_ctx *ctx, struct vsir_program *program, static void sm1_generate_vsir_instr_swizzle(struct hlsl_ctx *ctx, struct vsir_program *program,
struct hlsl_ir_swizzle *swizzle_instr) struct hlsl_ir_swizzle *swizzle_instr)
{ {
@ -7112,6 +7220,10 @@ static bool sm1_generate_vsir_instr(struct hlsl_ctx *ctx, struct hlsl_ir_node *i
sm1_generate_vsir_instr_load(ctx, program, hlsl_ir_load(instr)); sm1_generate_vsir_instr_load(ctx, program, hlsl_ir_load(instr));
return true; return true;
case HLSL_IR_RESOURCE_LOAD:
sm1_generate_vsir_instr_resource_load(ctx, program, hlsl_ir_resource_load(instr));
return true;
case HLSL_IR_STORE: case HLSL_IR_STORE:
sm1_generate_vsir_instr_store(ctx, program, hlsl_ir_store(instr)); sm1_generate_vsir_instr_store(ctx, program, hlsl_ir_store(instr));
return true; return true;