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vkd3d-shader/tpf: Use lookup table for opcode_info_from_sm4().

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Makes get_opcode_info() and thus, tpf reading a little faster.
This commit is contained in:
Francisco Casas
2023-07-27 18:34:26 -04:00
committed by Alexandre Julliard
parent 88b644a11d
commit 014960b64b
Notes: Alexandre Julliard 2023-10-05 22:38:01 +02:00 
Approved-by: Giovanni Mascellani (@giomasce)
Approved-by: Henri Verbeet (@hverbeet)
Approved-by: Alexandre Julliard (@julliard)
Merge-Request: https://gitlab.winehq.org/wine/vkd3d/-/merge_requests/387
1 changed files with 302 additions and 297 deletions
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105
libs/vkd3d-shader/tpf.c
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@@ -383,6 +383,8 @@ enum vkd3d_sm4_opcode
VKD3D_SM5_OP_SAMPLE_GRAD_CL_S = 0xe8, VKD3D_SM5_OP_SAMPLE_GRAD_CL_S = 0xe8,
VKD3D_SM5_OP_SAMPLE_C_CL_S = 0xe9, VKD3D_SM5_OP_SAMPLE_C_CL_S = 0xe9,
VKD3D_SM5_OP_CHECK_ACCESS_FULLY_MAPPED = 0xea, VKD3D_SM5_OP_CHECK_ACCESS_FULLY_MAPPED = 0xea,
VKD3D_SM4_OP_COUNT,
}; };
enum vkd3d_sm4_instruction_modifier enum vkd3d_sm4_instruction_modifier
@@ -607,6 +609,7 @@ struct sm4_index_range_array
struct vkd3d_sm4_lookup_tables struct vkd3d_sm4_lookup_tables
{ {
const struct vkd3d_sm4_opcode_info *opcode_info_from_sm4[VKD3D_SM4_OP_COUNT];
const struct vkd3d_sm4_register_type_info *register_type_info_from_sm4[VKD3D_SM4_REGISTER_TYPE_COUNT]; const struct vkd3d_sm4_register_type_info *register_type_info_from_sm4[VKD3D_SM4_REGISTER_TYPE_COUNT];
const struct vkd3d_sm4_register_type_info *register_type_info_from_vkd3d[VKD3DSPR_COUNT]; const struct vkd3d_sm4_register_type_info *register_type_info_from_vkd3d[VKD3DSPR_COUNT];
}; };
@@ -1243,7 +1246,37 @@ static void shader_sm5_read_sync(struct vkd3d_shader_instruction *ins, uint32_t
ins->flags = (opcode_token & VKD3D_SM5_SYNC_FLAGS_MASK) >> VKD3D_SM5_SYNC_FLAGS_SHIFT; ins->flags = (opcode_token & VKD3D_SM5_SYNC_FLAGS_MASK) >> VKD3D_SM5_SYNC_FLAGS_SHIFT;
} }
/* struct vkd3d_sm4_register_type_info
{
enum vkd3d_sm4_register_type sm4_type;
enum vkd3d_shader_register_type vkd3d_type;
/* Swizzle type to be used for src registers when their dimension is VKD3D_SM4_DIMENSION_VEC4. */
enum vkd3d_sm4_swizzle_type default_src_swizzle_type;
};
static const enum vkd3d_shader_register_precision register_precision_table[] =
{
/* VKD3D_SM4_REGISTER_PRECISION_DEFAULT */ VKD3D_SHADER_REGISTER_PRECISION_DEFAULT,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_FLOAT_16 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_FLOAT_16,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_FLOAT_10 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_FLOAT_10,
/* UNKNOWN */ VKD3D_SHADER_REGISTER_PRECISION_INVALID,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_INT_16 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_INT_16,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_UINT_16 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_UINT_16,
};
struct tpf_writer
{
struct hlsl_ctx *ctx;
struct vkd3d_bytecode_buffer *buffer;
struct vkd3d_sm4_lookup_tables lookup;
};
static void init_sm4_lookup_tables(struct vkd3d_sm4_lookup_tables *lookup)
{
unsigned int i;
/*
* d -> VKD3D_DATA_DOUBLE * d -> VKD3D_DATA_DOUBLE
* f -> VKD3D_DATA_FLOAT * f -> VKD3D_DATA_FLOAT
* i -> VKD3D_DATA_INT * i -> VKD3D_DATA_INT
@@ -1253,8 +1286,8 @@ static void shader_sm5_read_sync(struct vkd3d_shader_instruction *ins, uint32_t
* S -> VKD3D_DATA_SAMPLER * S -> VKD3D_DATA_SAMPLER
* U -> VKD3D_DATA_UAV * U -> VKD3D_DATA_UAV
*/ */
static const struct vkd3d_sm4_opcode_info opcode_table[] = static const struct vkd3d_sm4_opcode_info opcode_table[] =
{ {
{VKD3D_SM4_OP_ADD, VKD3DSIH_ADD, "f", "ff"}, {VKD3D_SM4_OP_ADD, VKD3DSIH_ADD, "f", "ff"},
{VKD3D_SM4_OP_AND, VKD3DSIH_AND, "u", "uu"}, {VKD3D_SM4_OP_AND, VKD3DSIH_AND, "u", "uu"},
{VKD3D_SM4_OP_BREAK, VKD3DSIH_BREAK, "", ""}, {VKD3D_SM4_OP_BREAK, VKD3DSIH_BREAK, "", ""},
@@ -1522,51 +1555,7 @@ static const struct vkd3d_sm4_opcode_info opcode_table[] =
{VKD3D_SM5_OP_SAMPLE_GRAD_CL_S, VKD3DSIH_SAMPLE_GRAD_CL_S, "uu", "fRSfff"}, {VKD3D_SM5_OP_SAMPLE_GRAD_CL_S, VKD3DSIH_SAMPLE_GRAD_CL_S, "uu", "fRSfff"},
{VKD3D_SM5_OP_SAMPLE_C_CL_S, VKD3DSIH_SAMPLE_C_CL_S, "fu", "fRSff"}, {VKD3D_SM5_OP_SAMPLE_C_CL_S, VKD3DSIH_SAMPLE_C_CL_S, "fu", "fRSff"},
{VKD3D_SM5_OP_CHECK_ACCESS_FULLY_MAPPED, VKD3DSIH_CHECK_ACCESS_FULLY_MAPPED, "u", "u"}, {VKD3D_SM5_OP_CHECK_ACCESS_FULLY_MAPPED, VKD3DSIH_CHECK_ACCESS_FULLY_MAPPED, "u", "u"},
}; };
struct vkd3d_sm4_register_type_info
{
enum vkd3d_sm4_register_type sm4_type;
enum vkd3d_shader_register_type vkd3d_type;
/* Swizzle type to be used for src registers when their dimension is VKD3D_SM4_DIMENSION_VEC4. */
enum vkd3d_sm4_swizzle_type default_src_swizzle_type;
};
static const enum vkd3d_shader_register_precision register_precision_table[] =
{
/* VKD3D_SM4_REGISTER_PRECISION_DEFAULT */ VKD3D_SHADER_REGISTER_PRECISION_DEFAULT,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_FLOAT_16 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_FLOAT_16,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_FLOAT_10 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_FLOAT_10,
/* UNKNOWN */ VKD3D_SHADER_REGISTER_PRECISION_INVALID,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_INT_16 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_INT_16,
/* VKD3D_SM4_REGISTER_PRECISION_MIN_UINT_16 */ VKD3D_SHADER_REGISTER_PRECISION_MIN_UINT_16,
};
struct tpf_writer
{
struct hlsl_ctx *ctx;
struct vkd3d_bytecode_buffer *buffer;
struct vkd3d_sm4_lookup_tables lookup;
};
static const struct vkd3d_sm4_opcode_info *get_opcode_info(enum vkd3d_sm4_opcode opcode)
{
unsigned int i;
for (i = 0; i < sizeof(opcode_table) / sizeof(*opcode_table); ++i)
{
if (opcode == opcode_table[i].opcode)
return &opcode_table[i];
}
return NULL;
}
static void init_sm4_lookup_tables(struct vkd3d_sm4_lookup_tables *lookup)
{
const struct vkd3d_sm4_register_type_info *info;
unsigned int i;
static const struct vkd3d_sm4_register_type_info register_type_table[] = static const struct vkd3d_sm4_register_type_info register_type_table[] =
{ {
@@ -1610,9 +1599,17 @@ static void init_sm4_lookup_tables(struct vkd3d_sm4_lookup_tables *lookup)
memset(lookup, 0, sizeof(*lookup)); memset(lookup, 0, sizeof(*lookup));
for (i = 0; i < ARRAY_SIZE(opcode_table); ++i)
{
const struct vkd3d_sm4_opcode_info *info = &opcode_table[i];
lookup->opcode_info_from_sm4[info->opcode] = info;
}
for (i = 0; i < ARRAY_SIZE(register_type_table); ++i) for (i = 0; i < ARRAY_SIZE(register_type_table); ++i)
{ {
info = &register_type_table[i]; const struct vkd3d_sm4_register_type_info *info = &register_type_table[i];
lookup->register_type_info_from_sm4[info->sm4_type] = info; lookup->register_type_info_from_sm4[info->sm4_type] = info;
lookup->register_type_info_from_vkd3d[info->vkd3d_type] = info; lookup->register_type_info_from_vkd3d[info->vkd3d_type] = info;
} }
@@ -1625,6 +1622,14 @@ static void tpf_writer_init(struct tpf_writer *tpf, struct hlsl_ctx *ctx, struct
init_sm4_lookup_tables(&tpf->lookup); init_sm4_lookup_tables(&tpf->lookup);
} }
static const struct vkd3d_sm4_opcode_info *get_info_from_sm4_opcode(
const struct vkd3d_sm4_lookup_tables *lookup, enum vkd3d_sm4_opcode sm4_opcode)
{
if (sm4_opcode >= VKD3D_SM4_OP_COUNT)
return NULL;
return lookup->opcode_info_from_sm4[sm4_opcode];
}
static const struct vkd3d_sm4_register_type_info *get_info_from_sm4_register_type( static const struct vkd3d_sm4_register_type_info *get_info_from_sm4_register_type(
const struct vkd3d_sm4_lookup_tables *lookup, enum vkd3d_sm4_register_type sm4_type) const struct vkd3d_sm4_lookup_tables *lookup, enum vkd3d_sm4_register_type sm4_type)
{ {
@@ -2360,7 +2365,7 @@ static void shader_sm4_read_instruction(struct vkd3d_shader_sm4_parser *sm4, str
} }
--len; --len;
if (!(opcode_info = get_opcode_info(opcode))) if (!(opcode_info = get_info_from_sm4_opcode(&sm4->lookup, opcode)))
{ {
FIXME("Unrecognized opcode %#x, opcode_token 0x%08x.\n", opcode, opcode_token); FIXME("Unrecognized opcode %#x, opcode_token 0x%08x.\n", opcode, opcode_token);
ins->handler_idx = VKD3DSIH_INVALID; ins->handler_idx = VKD3DSIH_INVALID;