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vkd3d/libs/vkd3d-shader/ir.c

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vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
/*
* Copyright 2023 Conor McCarthy for CodeWeavers
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include "vkd3d_shader_private.h"
static inline bool shader_register_is_phase_instance_id(const struct vkd3d_shader_register *reg)
{
return reg->type == VKD3DSPR_FORKINSTID || reg->type == VKD3DSPR_JOININSTID;
}
static bool shader_instruction_is_dcl(const struct vkd3d_shader_instruction *ins)
{
return (VKD3DSIH_DCL <= ins->handler_idx && ins->handler_idx <= VKD3DSIH_DCL_VERTICES_OUT)
|| ins->handler_idx == VKD3DSIH_HS_DECLS;
}
static void vkd3d_shader_instruction_make_nop(struct vkd3d_shader_instruction *ins)
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
struct vkd3d_shader_location location = ins->location;
vsir_instruction_init(ins, &location, VKD3DSIH_NOP);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
}
static void shader_register_eliminate_phase_addressing(struct vkd3d_shader_register *reg,
unsigned int instance_id)
{
unsigned int i;
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
for (i = 0; i < reg->idx_count; ++i)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
if (reg->idx[i].rel_addr && shader_register_is_phase_instance_id(&reg->idx[i].rel_addr->reg))
{
reg->idx[i].rel_addr = NULL;
reg->idx[i].offset += instance_id;
}
}
}
static void shader_instruction_eliminate_phase_instance_id(struct vkd3d_shader_instruction *ins,
unsigned int instance_id)
{
struct vkd3d_shader_register *reg;
unsigned int i;
for (i = 0; i < ins->src_count; ++i)
{
reg = (struct vkd3d_shader_register *)&ins->src[i].reg;
if (shader_register_is_phase_instance_id(reg))
{
vkd3d-shader/ir: Use vsir_register_init() to initialize a register.
2023-11-08 02:11:39 -08:00
vsir_register_init(reg, VKD3DSPR_IMMCONST, reg->data_type, 0);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
reg->u.immconst_uint[0] = instance_id;
continue;
}
shader_register_eliminate_phase_addressing(reg, instance_id);
}
for (i = 0; i < ins->dst_count; ++i)
shader_register_eliminate_phase_addressing((struct vkd3d_shader_register *)&ins->dst[i].reg, instance_id);
}
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
static const struct vkd3d_shader_varying_map *find_varying_map(
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
const struct vkd3d_shader_varying_map_info *varying_map, unsigned int signature_idx)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
unsigned int i;
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
for (i = 0; i < varying_map->varying_count; ++i)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
if (varying_map->varying_map[i].output_signature_index == signature_idx)
return &varying_map->varying_map[i];
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
}
return NULL;
}
static enum vkd3d_result remap_output_signature(struct vkd3d_shader_parser *parser,
const struct vkd3d_shader_compile_info *compile_info)
{
struct shader_signature *signature = &parser->shader_desc.output_signature;
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
const struct vkd3d_shader_varying_map_info *varying_map;
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
unsigned int i;
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
if (!(varying_map = vkd3d_find_struct(compile_info->next, VARYING_MAP_INFO)))
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
return VKD3D_OK;
for (i = 0; i < signature->element_count; ++i)
{
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
const struct vkd3d_shader_varying_map *map = find_varying_map(varying_map, i);
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
struct signature_element *e = &signature->elements[i];
if (map)
{
unsigned int input_mask = map->input_mask;
e->target_location = map->input_register_index;
/* It is illegal in Vulkan if the next shader uses the same varying
* location with a different mask. */
if (input_mask && input_mask != e->mask)
{
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED,
"Aborting due to not yet implemented feature: "
"Output mask %#x does not match input mask %#x.",
e->mask, input_mask);
return VKD3D_ERROR_NOT_IMPLEMENTED;
}
}
else
{
vkd3d-shader/spirv: Make output varyings not consumed by the next stage private variables.
2023-07-31 10:46:55 -07:00
e->target_location = SIGNATURE_TARGET_LOCATION_UNUSED;
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
}
}
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
for (i = 0; i < varying_map->varying_count; ++i)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
vkd3d-shader: Rename vkd3d_shader_next_stage_info to vkd3d_shader_varying_map_info. It was originally intended that this structure could hold other information about the next stage which compilation might depend on. For example, compilation to GLSL needs to know the type of the next shader in some circumstances. That was never actualized, and since the API is fixed at this point for 1.9, it makes the most sense to rename the structure to match its actual scope. The documentation was written and arranged to imply that the structure would hold other information about the next shader than the varying map; this is changed accordingly as well.
2023-09-19 14:04:53 -07:00
if (varying_map->varying_map[i].output_signature_index >= signature->element_count)
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
{
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED,
"Aborting due to not yet implemented feature: "
"The next stage consumes varyings not written by this stage.");
return VKD3D_ERROR_NOT_IMPLEMENTED;
}
}
return VKD3D_OK;
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct hull_flattener
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct vkd3d_shader_instruction_array instructions;
unsigned int max_temp_count;
unsigned int temp_dcl_idx;
unsigned int instance_count;
unsigned int phase_body_idx;
enum vkd3d_shader_opcode phase;
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
struct vkd3d_shader_location last_ret_location;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
};
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static bool flattener_is_in_fork_or_join_phase(const struct hull_flattener *flattener)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
return flattener->phase == VKD3DSIH_HS_FORK_PHASE || flattener->phase == VKD3DSIH_HS_JOIN_PHASE;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
}
struct shader_phase_location
{
unsigned int index;
unsigned int instance_count;
unsigned int instruction_count;
};
struct shader_phase_location_array
{
/* Unlikely worst case: one phase for each component of each output register. */
struct shader_phase_location locations[MAX_REG_OUTPUT * VKD3D_VEC4_SIZE];
unsigned int count;
};
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static void flattener_eliminate_phase_related_dcls(struct hull_flattener *normaliser,
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
unsigned int index, struct shader_phase_location_array *locations)
{
struct vkd3d_shader_instruction *ins = &normaliser->instructions.elements[index];
struct shader_phase_location *loc;
bool b;
if (ins->handler_idx == VKD3DSIH_HS_FORK_PHASE || ins->handler_idx == VKD3DSIH_HS_JOIN_PHASE)
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
b = flattener_is_in_fork_or_join_phase(normaliser);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
/* Reset the phase info. */
normaliser->phase_body_idx = ~0u;
normaliser->phase = ins->handler_idx;
normaliser->instance_count = 1;
/* Leave the first occurrence and delete the rest. */
if (b)
vkd3d_shader_instruction_make_nop(ins);
return;
}
else if (ins->handler_idx == VKD3DSIH_DCL_HS_FORK_PHASE_INSTANCE_COUNT
|| ins->handler_idx == VKD3DSIH_DCL_HS_JOIN_PHASE_INSTANCE_COUNT)
{
normaliser->instance_count = ins->declaration.count + !ins->declaration.count;
vkd3d_shader_instruction_make_nop(ins);
return;
}
else if (ins->handler_idx == VKD3DSIH_DCL_INPUT && shader_register_is_phase_instance_id(
&ins->declaration.dst.reg))
{
vkd3d_shader_instruction_make_nop(ins);
return;
}
else if (ins->handler_idx == VKD3DSIH_DCL_TEMPS && normaliser->phase != VKD3DSIH_INVALID)
{
/* Leave only the first temp declaration and set it to the max count later. */
if (!normaliser->max_temp_count)
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
{
normaliser->max_temp_count = ins->declaration.count;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
normaliser->temp_dcl_idx = index;
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
}
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
else
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
{
normaliser->max_temp_count = max(normaliser->max_temp_count, ins->declaration.count);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Correctly compute the TEMP count after hull shader flattening. The previous computation was incorrect because the count was taken after resetting it to zero (as part of setting the instruction to NOP).
2023-11-16 14:07:27 -08:00
}
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return;
}
if (normaliser->phase == VKD3DSIH_INVALID || shader_instruction_is_dcl(ins))
return;
if (normaliser->phase_body_idx == ~0u)
normaliser->phase_body_idx = index;
if (ins->handler_idx == VKD3DSIH_RET)
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
normaliser->last_ret_location = ins->location;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d_shader_instruction_make_nop(ins);
if (locations->count >= ARRAY_SIZE(locations->locations))
{
FIXME("Insufficient space for phase location.\n");
return;
}
loc = &locations->locations[locations->count++];
loc->index = normaliser->phase_body_idx;
loc->instance_count = normaliser->instance_count;
loc->instruction_count = index - normaliser->phase_body_idx;
}
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static enum vkd3d_result flattener_flatten_phases(struct hull_flattener *normaliser,
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
struct shader_phase_location_array *locations)
{
struct shader_phase_location *loc;
unsigned int i, j, k, end, count;
for (i = 0, count = 0; i < locations->count; ++i)
count += (locations->locations[i].instance_count - 1) * locations->locations[i].instruction_count;
if (!shader_instruction_array_reserve(&normaliser->instructions, normaliser->instructions.count + count))
return VKD3D_ERROR_OUT_OF_MEMORY;
end = normaliser->instructions.count;
normaliser->instructions.count += count;
for (i = locations->count; i > 0; --i)
{
loc = &locations->locations[i - 1];
j = loc->index + loc->instruction_count;
memmove(&normaliser->instructions.elements[j + count], &normaliser->instructions.elements[j],
(end - j) * sizeof(*normaliser->instructions.elements));
end = j;
count -= (loc->instance_count - 1) * loc->instruction_count;
loc->index += count;
}
for (i = 0, count = 0; i < locations->count; ++i)
{
loc = &locations->locations[i];
/* Make a copy of the non-dcl instructions for each instance. */
for (j = 1; j < loc->instance_count; ++j)
{
for (k = 0; k < loc->instruction_count; ++k)
{
if (!shader_instruction_array_clone_instruction(&normaliser->instructions,
loc->index + loc->instruction_count * j + k, loc->index + k))
return VKD3D_ERROR_OUT_OF_MEMORY;
}
}
/* Replace each reference to the instance id with a constant instance id. */
for (j = 0; j < loc->instance_count; ++j)
{
for (k = 0; k < loc->instruction_count; ++k)
shader_instruction_eliminate_phase_instance_id(
&normaliser->instructions.elements[loc->index + loc->instruction_count * j + k], j);
}
}
return VKD3D_OK;
}
vkd3d-shader: Rename shader_register_init() to vsir_register_init().
2023-08-29 10:20:44 -07:00
void vsir_register_init(struct vkd3d_shader_register *reg, enum vkd3d_shader_register_type reg_type,
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
enum vkd3d_data_type data_type, unsigned int idx_count)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
reg->type = reg_type;
reg->precision = VKD3D_SHADER_REGISTER_PRECISION_DEFAULT;
reg->non_uniform = false;
reg->data_type = data_type;
reg->idx[0].offset = ~0u;
reg->idx[0].rel_addr = NULL;
vkd3d-shader/dxil: Implement the DXIL GEP instruction.
2023-11-12 22:52:45 -08:00
reg->idx[0].is_in_bounds = false;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
reg->idx[1].offset = ~0u;
reg->idx[1].rel_addr = NULL;
vkd3d-shader/dxil: Implement the DXIL GEP instruction.
2023-11-12 22:52:45 -08:00
reg->idx[1].is_in_bounds = false;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
reg->idx[2].offset = ~0u;
reg->idx[2].rel_addr = NULL;
vkd3d-shader/dxil: Implement the DXIL GEP instruction.
2023-11-12 22:52:45 -08:00
reg->idx[2].is_in_bounds = false;
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
reg->idx_count = idx_count;
vkd3d-shader: Turn vkd3d_shader_register.immconst_type into vkd3d_shader_register.dimension.
2023-08-14 10:21:41 -07:00
reg->dimension = VSIR_DIMENSION_SCALAR;
vkd3d-shader/dxil: Implement the DXIL LOAD instruction.
2023-11-21 18:42:23 -08:00
reg->alignment = 0;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
}
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
void vsir_instruction_init(struct vkd3d_shader_instruction *ins, const struct vkd3d_shader_location *location,
enum vkd3d_shader_opcode handler_idx)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
memset(ins, 0, sizeof(*ins));
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
ins->location = *location;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
ins->handler_idx = handler_idx;
}
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
static enum vkd3d_result instruction_array_flatten_hull_shader_phases(struct vkd3d_shader_instruction_array *src_instructions)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct hull_flattener flattener = {*src_instructions};
struct vkd3d_shader_instruction_array *instructions;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
struct shader_phase_location_array locations;
enum vkd3d_result result = VKD3D_OK;
unsigned int i;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
instructions = &flattener.instructions;
flattener.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
for (i = 0, locations.count = 0; i < instructions->count; ++i)
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
flattener_eliminate_phase_related_dcls(&flattener, i, &locations);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if ((result = flattener_flatten_phases(&flattener, &locations)) < 0)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return result;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (flattener.phase != VKD3DSIH_INVALID)
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (flattener.temp_dcl_idx)
instructions->elements[flattener.temp_dcl_idx].declaration.count = flattener.max_temp_count;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (!shader_instruction_array_reserve(&flattener.instructions, flattener.instructions.count + 1))
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return VKD3D_ERROR_OUT_OF_MEMORY;
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(&instructions->elements[instructions->count++], &flattener.last_ret_location, VKD3DSIH_RET);
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = flattener.instructions;
vkd3d-shader/ir: Merge all shader IR fork and join phases into a single phase. Normalise the incoming vkd3d_shader_instruction IR to the shader model 6 pattern. This allows generation of a single patch constant function in SPIR-V.
2023-02-28 17:59:28 -08:00
return result;
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct control_point_normaliser
{
struct vkd3d_shader_instruction_array instructions;
enum vkd3d_shader_opcode phase;
struct vkd3d_shader_src_param *outpointid_param;
};
static bool control_point_normaliser_is_in_control_point_phase(const struct control_point_normaliser *normaliser)
{
return normaliser->phase == VKD3DSIH_HS_CONTROL_POINT_PHASE;
}
static struct vkd3d_shader_src_param *instruction_array_create_outpointid_param(
struct vkd3d_shader_instruction_array *instructions)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
struct vkd3d_shader_src_param *rel_addr;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (!(rel_addr = shader_src_param_allocator_get(&instructions->src_params, 1)))
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
return NULL;
vkd3d-shader: Rename shader_register_init() to vsir_register_init().
2023-08-29 10:20:44 -07:00
vsir_register_init(&rel_addr->reg, VKD3DSPR_OUTPOINTID, VKD3D_DATA_UINT, 0);
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
rel_addr->swizzle = 0;
rel_addr->modifiers = 0;
return rel_addr;
}
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
static void shader_dst_param_normalise_outpointid(struct vkd3d_shader_dst_param *dst_param,
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct control_point_normaliser *normaliser)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
struct vkd3d_shader_register *reg = &dst_param->reg;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (control_point_normaliser_is_in_control_point_phase(normaliser) && reg->type == VKD3DSPR_OUTPUT)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
/* The TPF reader validates idx_count. */
assert(reg->idx_count == 1);
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
reg->idx[1] = reg->idx[0];
/* The control point id param is implicit here. Avoid later complications by inserting it. */
reg->idx[0].offset = 0;
reg->idx[0].rel_addr = normaliser->outpointid_param;
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
++reg->idx_count;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
}
}
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
static void shader_dst_param_io_init(struct vkd3d_shader_dst_param *param, const struct signature_element *e,
enum vkd3d_shader_register_type reg_type, unsigned int idx_count)
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
{
param->write_mask = e->mask;
param->modifiers = 0;
param->shift = 0;
vkd3d-shader: Rename shader_register_init() to vsir_register_init().
2023-08-29 10:20:44 -07:00
vsir_register_init(&param->reg, reg_type, vkd3d_data_type_from_component_type(e->component_type), idx_count);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
static enum vkd3d_result control_point_normaliser_emit_hs_input(struct control_point_normaliser *normaliser,
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
const struct shader_signature *s, unsigned int input_control_point_count, unsigned int dst,
const struct vkd3d_shader_location *location)
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
{
struct vkd3d_shader_instruction *ins;
struct vkd3d_shader_dst_param *param;
vkd3d-shader: Introduce an internal shader signature structure. A register count is required for Shader Model 6 signatures, including those normalised from earlier models.
2023-04-03 23:22:57 -07:00
const struct signature_element *e;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
unsigned int i, count;
for (i = 0, count = 1; i < s->element_count; ++i)
count += !!s->elements[i].used_mask;
if (!shader_instruction_array_reserve(&normaliser->instructions, normaliser->instructions.count + count))
return VKD3D_ERROR_OUT_OF_MEMORY;
memmove(&normaliser->instructions.elements[dst + count], &normaliser->instructions.elements[dst],
(normaliser->instructions.count - dst) * sizeof(*normaliser->instructions.elements));
normaliser->instructions.count += count;
ins = &normaliser->instructions.elements[dst];
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(ins, location, VKD3DSIH_HS_CONTROL_POINT_PHASE);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
ins->flags = 1;
++ins;
for (i = 0; i < s->element_count; ++i)
{
e = &s->elements[i];
if (!e->used_mask)
continue;
if (e->sysval_semantic != VKD3D_SHADER_SV_NONE)
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(ins, location, VKD3DSIH_DCL_INPUT_SIV);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
param = &ins->declaration.register_semantic.reg;
ins->declaration.register_semantic.sysval_semantic = vkd3d_siv_from_sysval(e->sysval_semantic);
}
else
{
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
vsir_instruction_init(ins, location, VKD3DSIH_DCL_INPUT);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
param = &ins->declaration.dst;
}
vkd3d-shader/tpf: Validate input/output register index counts.
2023-05-03 00:10:37 -07:00
shader_dst_param_io_init(param, e, VKD3DSPR_INPUT, 2);
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
param->reg.idx[0].offset = input_control_point_count;
vkd3d-shader/ir: Synthesize HS inputs with the register index and write mask of the signature element. This pass was written as if to output normalized I/O, but it runs before the I/O normalization pass. Fixes: 98b5e2c6e01199d714d18fccfe54826a680aecbf
2023-10-24 14:55:16 -07:00
param->reg.idx[1].offset = e->register_index;
param->write_mask = e->mask;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
++ins;
}
return VKD3D_OK;
}
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
static enum vkd3d_result instruction_array_normalise_hull_shader_control_point_io(
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct vkd3d_shader_instruction_array *src_instructions, const struct shader_signature *input_signature)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
struct vkd3d_shader_instruction_array *instructions;
struct control_point_normaliser normaliser;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
unsigned int input_control_point_count;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
struct vkd3d_shader_instruction *ins;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
enum vkd3d_result ret;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
unsigned int i, j;
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
if (!(normaliser.outpointid_param = instruction_array_create_outpointid_param(src_instructions)))
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
ERR("Failed to allocate src param.\n");
return VKD3D_ERROR_OUT_OF_MEMORY;
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
normaliser.instructions = *src_instructions;
instructions = &normaliser.instructions;
normaliser.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
for (i = 0; i < normaliser.instructions.count; ++i)
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
{
ins = &instructions->elements[i];
switch (ins->handler_idx)
{
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
normaliser.phase = ins->handler_idx;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
break;
default:
if (shader_instruction_is_dcl(ins))
break;
for (j = 0; j < ins->dst_count; ++j)
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
shader_dst_param_normalise_outpointid((struct vkd3d_shader_dst_param *)&ins->dst[j], &normaliser);
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
break;
}
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
normaliser.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
input_control_point_count = 1;
for (i = 0; i < instructions->count; ++i)
{
ins = &instructions->elements[i];
switch (ins->handler_idx)
{
case VKD3DSIH_DCL_INPUT_CONTROL_POINT_COUNT:
input_control_point_count = ins->declaration.count;
break;
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = normaliser.instructions;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
return VKD3D_OK;
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
ret = control_point_normaliser_emit_hs_input(&normaliser, input_signature,
vkd3d-shader: Embed the parsing location in vkd3d_shader_instruction. So that it can be used for printing meaningful error locations by downstream processors.
2023-09-05 02:31:31 -07:00
input_control_point_count, i, &ins->location);
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = normaliser.instructions;
return ret;
vkd3d-shader/ir: Insert hull shader control point input declarations if no control point phase is defined. The SPIR-V backend will emit a default control point phase. Inserting inputs into the IR allows handling of declarations via the usual path instead of an ad hoc implementation which may not match later changes to input handling.
2023-04-04 00:28:48 -07:00
default:
break;
}
}
vkd3d-shader/ir: Eliminate struct vkd3d_shader_normaliser.
2023-05-05 00:23:56 -07:00
*src_instructions = normaliser.instructions;
vkd3d-shader/ir: Normalise control point phase output registers to include the control point id. In SPIR-V the address must include the invocation id, but in TPF it is implicit. Move the register index up one slot and insert an OUTPOINTID relative address.
2023-04-04 00:55:05 -07:00
return VKD3D_OK;
}
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
struct io_normaliser
{
struct vkd3d_shader_instruction_array instructions;
enum vkd3d_shader_type shader_type;
struct shader_signature *input_signature;
struct shader_signature *output_signature;
struct shader_signature *patch_constant_signature;
unsigned int max_temp_count;
unsigned int temp_dcl_idx;
unsigned int instance_count;
unsigned int phase_body_idx;
enum vkd3d_shader_opcode phase;
unsigned int output_control_point_count;
struct vkd3d_shader_src_param *outpointid_param;
struct vkd3d_shader_dst_param *input_dcl_params[MAX_REG_OUTPUT];
struct vkd3d_shader_dst_param *output_dcl_params[MAX_REG_OUTPUT];
struct vkd3d_shader_dst_param *pc_dcl_params[MAX_REG_OUTPUT];
uint8_t input_range_map[MAX_REG_OUTPUT][VKD3D_VEC4_SIZE];
uint8_t output_range_map[MAX_REG_OUTPUT][VKD3D_VEC4_SIZE];
uint8_t pc_range_map[MAX_REG_OUTPUT][VKD3D_VEC4_SIZE];
vkd3d-shader/ir: Check for vocp usage during IR normalization. The hull shader barrier used for this was broken by I/O normalization, since vocp is no longer exposed to the spirv backend. Restore this barrier by checking for vocp during normalization instead.
2023-07-16 21:34:04 -07:00
bool use_vocp;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
};
static bool io_normaliser_is_in_fork_or_join_phase(const struct io_normaliser *normaliser)
{
return normaliser->phase == VKD3DSIH_HS_FORK_PHASE || normaliser->phase == VKD3DSIH_HS_JOIN_PHASE;
}
static bool io_normaliser_is_in_control_point_phase(const struct io_normaliser *normaliser)
{
return normaliser->phase == VKD3DSIH_HS_CONTROL_POINT_PHASE;
}
static unsigned int shader_signature_find_element_for_reg(const struct shader_signature *signature,
unsigned int reg_idx, unsigned int write_mask)
{
unsigned int i;
for (i = 0; i < signature->element_count; ++i)
{
struct signature_element *e = &signature->elements[i];
if (e->register_index <= reg_idx && e->register_index + e->register_count > reg_idx
&& (e->mask & write_mask) == write_mask)
{
return i;
}
}
/* Validated in the TPF reader. */
vkd3d_unreachable();
}
vkd3d-shader/tpf: Set the interpolation mode for signature elements.
2023-10-19 19:34:41 -07:00
struct signature_element *vsir_signature_find_element_for_reg(const struct shader_signature *signature,
unsigned int reg_idx, unsigned int write_mask)
{
return &signature->elements[shader_signature_find_element_for_reg(signature, reg_idx, write_mask)];
}
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
static unsigned int range_map_get_register_count(uint8_t range_map[][VKD3D_VEC4_SIZE],
unsigned int register_idx, unsigned int write_mask)
{
return range_map[register_idx][vkd3d_write_mask_get_component_idx(write_mask)];
}
static void range_map_set_register_range(uint8_t range_map[][VKD3D_VEC4_SIZE], unsigned int register_idx,
unsigned int register_count, unsigned int write_mask, bool is_dcl_indexrange)
{
unsigned int i, j, r, c, component_idx, component_count;
assert(write_mask <= VKD3DSP_WRITEMASK_ALL);
component_idx = vkd3d_write_mask_get_component_idx(write_mask);
component_count = vkd3d_write_mask_component_count(write_mask);
assert(register_idx < MAX_REG_OUTPUT && MAX_REG_OUTPUT - register_idx >= register_count);
if (range_map[register_idx][component_idx] > register_count && is_dcl_indexrange)
{
/* Validated in the TPF reader. */
assert(range_map[register_idx][component_idx] != UINT8_MAX);
return;
}
if (range_map[register_idx][component_idx] == register_count)
{
/* Already done. This happens when fxc splits a register declaration by
* component(s). The dcl_indexrange instructions are split too. */
return;
}
range_map[register_idx][component_idx] = register_count;
for (i = 0; i < register_count; ++i)
{
r = register_idx + i;
for (j = !i; j < component_count; ++j)
{
c = component_idx + j;
/* A synthetic patch constant range which overlaps an existing range can start upstream of it
* for fork/join phase instancing, but ranges declared by dcl_indexrange should not overlap.
* The latter is validated in the TPF reader. */
assert(!range_map[r][c] || !is_dcl_indexrange);
range_map[r][c] = UINT8_MAX;
}
}
}
static void io_normaliser_add_index_range(struct io_normaliser *normaliser,
const struct vkd3d_shader_instruction *ins)
{
const struct vkd3d_shader_index_range *range = &ins->declaration.index_range;
const struct vkd3d_shader_register *reg = &range->dst.reg;
unsigned int reg_idx, write_mask, element_idx;
const struct shader_signature *signature;
uint8_t (*range_map)[VKD3D_VEC4_SIZE];
switch (reg->type)
{
case VKD3DSPR_INPUT:
case VKD3DSPR_INCONTROLPOINT:
range_map = normaliser->input_range_map;
signature = normaliser->input_signature;
break;
case VKD3DSPR_OUTCONTROLPOINT:
range_map = normaliser->output_range_map;
signature = normaliser->output_signature;
break;
case VKD3DSPR_OUTPUT:
if (!io_normaliser_is_in_fork_or_join_phase(normaliser))
{
range_map = normaliser->output_range_map;
signature = normaliser->output_signature;
break;
}
/* fall through */
case VKD3DSPR_PATCHCONST:
range_map = normaliser->pc_range_map;
signature = normaliser->patch_constant_signature;
break;
default:
/* Validated in the TPF reader. */
vkd3d_unreachable();
}
reg_idx = reg->idx[reg->idx_count - 1].offset;
write_mask = range->dst.write_mask;
element_idx = shader_signature_find_element_for_reg(signature, reg_idx, write_mask);
range_map_set_register_range(range_map, reg_idx, range->register_count,
signature->elements[element_idx].mask, true);
}
static int signature_element_mask_compare(const void *a, const void *b)
{
const struct signature_element *e = a, *f = b;
int ret;
return (ret = vkd3d_u32_compare(e->mask, f->mask)) ? ret : vkd3d_u32_compare(e->register_index, f->register_index);
}
static bool sysval_semantics_should_merge(const struct signature_element *e, const struct signature_element *f)
{
if (e->sysval_semantic < VKD3D_SHADER_SV_TESS_FACTOR_QUADEDGE
|| e->sysval_semantic > VKD3D_SHADER_SV_TESS_FACTOR_LINEDEN)
return false;
return e->sysval_semantic == f->sysval_semantic
/* Line detail and density must be merged together to match the SPIR-V array.
* This deletes one of the two sysvals, but these are not used. */
|| (e->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDET
&& f->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDEN)
|| (e->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDEN
&& f->sysval_semantic == VKD3D_SHADER_SV_TESS_FACTOR_LINEDET);
}
/* Merge tess factor sysvals because they are an array in SPIR-V. */
static void shader_signature_map_patch_constant_index_ranges(struct shader_signature *s,
uint8_t range_map[][VKD3D_VEC4_SIZE])
{
struct signature_element *e, *f;
unsigned int i, j, register_count;
qsort(s->elements, s->element_count, sizeof(s->elements[0]), signature_element_mask_compare);
for (i = 0; i < s->element_count; i += register_count)
{
e = &s->elements[i];
register_count = 1;
if (!e->sysval_semantic)
continue;
for (j = i + 1; j < s->element_count; ++j, ++register_count)
{
f = &s->elements[j];
if (f->register_index != e->register_index + register_count || !sysval_semantics_should_merge(e, f))
break;
}
if (register_count < 2)
continue;
range_map_set_register_range(range_map, e->register_index, register_count, e->mask, false);
}
}
static int signature_element_register_compare(const void *a, const void *b)
{
const struct signature_element *e = a, *f = b;
return vkd3d_u32_compare(e->register_index, f->register_index);
}
static int signature_element_index_compare(const void *a, const void *b)
{
const struct signature_element *e = a, *f = b;
return vkd3d_u32_compare(e->sort_index, f->sort_index);
}
static bool shader_signature_merge(struct shader_signature *s, uint8_t range_map[][VKD3D_VEC4_SIZE],
bool is_patch_constant)
{
unsigned int i, j, element_count, new_count, register_count;
struct signature_element *elements;
struct signature_element *e, *f;
element_count = s->element_count;
if (!(elements = vkd3d_malloc(element_count * sizeof(*elements))))
return false;
memcpy(elements, s->elements, element_count * sizeof(*elements));
qsort(elements, element_count, sizeof(elements[0]), signature_element_register_compare);
for (i = 0, new_count = 0; i < element_count; i = j, elements[new_count++] = *e)
{
e = &elements[i];
j = i + 1;
if (e->register_index == ~0u)
continue;
/* Do not merge if the register index will be relative-addressed. */
if (range_map_get_register_count(range_map, e->register_index, e->mask) > 1)
continue;
for (; j < element_count; ++j)
{
f = &elements[j];
/* Merge different components of the same register unless sysvals are different,
* or it will be relative-addressed. */
if (f->register_index != e->register_index || f->sysval_semantic != e->sysval_semantic
|| range_map_get_register_count(range_map, f->register_index, f->mask) > 1)
break;
TRACE("Merging %s, reg %u, mask %#x, sysval %#x with %s, mask %#x, sysval %#x.\n", e->semantic_name,
e->register_index, e->mask, e->sysval_semantic, f->semantic_name, f->mask, f->sysval_semantic);
assert(!(e->mask & f->mask));
e->mask |= f->mask;
e->used_mask |= f->used_mask;
e->semantic_index = min(e->semantic_index, f->semantic_index);
}
}
element_count = new_count;
vkd3d-shader/spirv: Take ownership of the shader signatures in spirv_compiler_create(). Fixes leakage of the replacement elements in shader_signature_merge().
2023-06-16 04:44:50 -07:00
vkd3d_free(s->elements);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
s->elements = elements;
s->element_count = element_count;
if (is_patch_constant)
shader_signature_map_patch_constant_index_ranges(s, range_map);
for (i = 0, new_count = 0; i < element_count; i += register_count, elements[new_count++] = *e)
{
e = &elements[i];
register_count = 1;
if (e->register_index >= MAX_REG_OUTPUT)
continue;
register_count = range_map_get_register_count(range_map, e->register_index, e->mask);
assert(register_count != UINT8_MAX);
register_count += !register_count;
if (register_count > 1)
{
TRACE("Merging %s, base reg %u, count %u.\n", e->semantic_name, e->register_index, register_count);
e->register_count = register_count;
}
}
element_count = new_count;
/* Restoring the original order is required for sensible trace output. */
qsort(elements, element_count, sizeof(elements[0]), signature_element_index_compare);
s->element_count = element_count;
return true;
}
static unsigned int shader_register_normalise_arrayed_addressing(struct vkd3d_shader_register *reg,
unsigned int id_idx, unsigned int register_index)
{
assert(id_idx < ARRAY_SIZE(reg->idx) - 1);
/* For a relative-addressed register index, move the id up a slot to separate it from the address,
* because rel_addr can be replaced with a constant offset in some cases. */
if (reg->idx[id_idx].rel_addr)
{
reg->idx[id_idx + 1].rel_addr = NULL;
reg->idx[id_idx + 1].offset = reg->idx[id_idx].offset;
reg->idx[id_idx].offset -= register_index;
++id_idx;
}
/* Otherwise we have no address for the arrayed register, so insert one. This happens e.g. where
* tessellation level registers are merged into an array because they're an array in SPIR-V. */
else
{
++id_idx;
memmove(&reg->idx[1], &reg->idx[0], id_idx * sizeof(reg->idx[0]));
reg->idx[0].rel_addr = NULL;
reg->idx[0].offset = reg->idx[id_idx].offset - register_index;
}
return id_idx;
}
static bool shader_dst_param_io_normalise(struct vkd3d_shader_dst_param *dst_param, bool is_io_dcl,
struct io_normaliser *normaliser)
{
unsigned int id_idx, reg_idx, write_mask, element_idx;
struct vkd3d_shader_register *reg = &dst_param->reg;
struct vkd3d_shader_dst_param **dcl_params;
const struct shader_signature *signature;
const struct signature_element *e;
if ((reg->type == VKD3DSPR_OUTPUT && io_normaliser_is_in_fork_or_join_phase(normaliser))
|| reg->type == VKD3DSPR_PATCHCONST)
{
signature = normaliser->patch_constant_signature;
/* Convert patch constant outputs to the patch constant register type to avoid the need
* to convert compiler symbols when accessed as inputs in a later stage. */
reg->type = VKD3DSPR_PATCHCONST;
dcl_params = normaliser->pc_dcl_params;
}
else if (reg->type == VKD3DSPR_OUTPUT || dst_param->reg.type == VKD3DSPR_COLOROUT)
{
signature = normaliser->output_signature;
vkd3d-shader/ir: Normalize all I/O registers to INPUT/OUTPUT/PATCHCONST. Specifically, map COLOROUT to OUTPUT, and map INCONTROLPOINT to INPUT for domain shaders as well as hull shaders. Obscure the non-existent differences from the view of the backend.
2023-07-16 21:56:22 -07:00
reg->type = VKD3DSPR_OUTPUT;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
dcl_params = normaliser->output_dcl_params;
}
else if (dst_param->reg.type == VKD3DSPR_INCONTROLPOINT || dst_param->reg.type == VKD3DSPR_INPUT)
{
signature = normaliser->input_signature;
vkd3d-shader/ir: Normalize all I/O registers to INPUT/OUTPUT/PATCHCONST. Specifically, map COLOROUT to OUTPUT, and map INCONTROLPOINT to INPUT for domain shaders as well as hull shaders. Obscure the non-existent differences from the view of the backend.
2023-07-16 21:56:22 -07:00
reg->type = VKD3DSPR_INPUT;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
dcl_params = normaliser->input_dcl_params;
}
else
{
return true;
}
id_idx = reg->idx_count - 1;
reg_idx = reg->idx[id_idx].offset;
write_mask = dst_param->write_mask;
element_idx = shader_signature_find_element_for_reg(signature, reg_idx, write_mask);
e = &signature->elements[element_idx];
dst_param->write_mask >>= vkd3d_write_mask_get_component_idx(e->mask);
if (is_io_dcl)
{
/* Validated in the TPF reader. */
assert(element_idx < ARRAY_SIZE(normaliser->input_dcl_params));
if (dcl_params[element_idx])
{
/* Merge split declarations into a single one. */
dcl_params[element_idx]->write_mask |= dst_param->write_mask;
/* Turn this into a nop. */
return false;
}
else
{
dcl_params[element_idx] = dst_param;
}
}
if (io_normaliser_is_in_control_point_phase(normaliser) && reg->type == VKD3DSPR_OUTPUT)
{
if (is_io_dcl)
{
/* Emit an array size for the control points for consistency with inputs. */
reg->idx[0].offset = normaliser->output_control_point_count;
}
else
{
/* The control point id param. */
assert(reg->idx[0].rel_addr);
}
id_idx = 1;
}
vkd3d-shader/spirv: Use register counts from the signature and shader desc.
2023-10-19 19:29:30 -07:00
if ((e->register_count > 1 || vsir_sysval_semantic_is_tess_factor(e->sysval_semantic)))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
if (is_io_dcl)
{
/* For control point I/O, idx 0 contains the control point count.
* Ensure it is moved up to the next slot. */
reg->idx[id_idx].offset = reg->idx[0].offset;
reg->idx[0].offset = e->register_count;
++id_idx;
}
else
{
id_idx = shader_register_normalise_arrayed_addressing(reg, id_idx, e->register_index);
}
}
/* Replace the register index with the signature element index */
reg->idx[id_idx].offset = element_idx;
reg->idx_count = id_idx + 1;
return true;
}
static void shader_src_param_io_normalise(struct vkd3d_shader_src_param *src_param,
struct io_normaliser *normaliser)
{
unsigned int i, id_idx, reg_idx, write_mask, element_idx, component_idx;
struct vkd3d_shader_register *reg = &src_param->reg;
const struct shader_signature *signature;
const struct signature_element *e;
/* Input/output registers from one phase can be used as inputs in
* subsequent phases. Specifically:
*
* - Control phase inputs are available as "vicp" in fork and join
* phases.
* - Control phase outputs are available as "vocp" in fork and join
* phases.
* - Fork phase patch constants are available as "vpc" in join
* phases.
*
* We handle "vicp" here by converting INCONTROLPOINT src registers to
* type INPUT so they match the control phase declarations. We handle
* "vocp" by converting OUTCONTROLPOINT registers to type OUTPUT.
* Merging fork and join phases handles "vpc". */
switch (reg->type)
{
case VKD3DSPR_PATCHCONST:
signature = normaliser->patch_constant_signature;
break;
case VKD3DSPR_INCONTROLPOINT:
vkd3d-shader/ir: Normalize all I/O registers to INPUT/OUTPUT/PATCHCONST. Specifically, map COLOROUT to OUTPUT, and map INCONTROLPOINT to INPUT for domain shaders as well as hull shaders. Obscure the non-existent differences from the view of the backend.
2023-07-16 21:56:22 -07:00
reg->type = VKD3DSPR_INPUT;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
/* fall through */
case VKD3DSPR_INPUT:
signature = normaliser->input_signature;
break;
case VKD3DSPR_OUTCONTROLPOINT:
vkd3d-shader/ir: Normalize all I/O registers to INPUT/OUTPUT/PATCHCONST. Specifically, map COLOROUT to OUTPUT, and map INCONTROLPOINT to INPUT for domain shaders as well as hull shaders. Obscure the non-existent differences from the view of the backend.
2023-07-16 21:56:22 -07:00
reg->type = VKD3DSPR_OUTPUT;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
/* fall through */
case VKD3DSPR_OUTPUT:
signature = normaliser->output_signature;
break;
default:
return;
}
id_idx = reg->idx_count - 1;
reg_idx = reg->idx[id_idx].offset;
write_mask = VKD3DSP_WRITEMASK_0 << vkd3d_swizzle_get_component(src_param->swizzle, 0);
element_idx = shader_signature_find_element_for_reg(signature, reg_idx, write_mask);
e = &signature->elements[element_idx];
vkd3d-shader/spirv: Use register counts from the signature and shader desc.
2023-10-19 19:29:30 -07:00
if ((e->register_count > 1 || vsir_sysval_semantic_is_tess_factor(e->sysval_semantic)))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
id_idx = shader_register_normalise_arrayed_addressing(reg, id_idx, e->register_index);
reg->idx[id_idx].offset = element_idx;
reg->idx_count = id_idx + 1;
if ((component_idx = vkd3d_write_mask_get_component_idx(e->mask)))
{
for (i = 0; i < VKD3D_VEC4_SIZE; ++i)
if (vkd3d_swizzle_get_component(src_param->swizzle, i))
src_param->swizzle -= component_idx << VKD3D_SHADER_SWIZZLE_SHIFT(i);
}
}
static void shader_instruction_normalise_io_params(struct vkd3d_shader_instruction *ins,
struct io_normaliser *normaliser)
{
struct vkd3d_shader_register *reg;
unsigned int i;
switch (ins->handler_idx)
{
case VKD3DSIH_DCL_INPUT:
if (normaliser->shader_type == VKD3D_SHADER_TYPE_HULL)
{
reg = &ins->declaration.dst.reg;
vkd3d-shader/ir: Check for vocp usage during IR normalization. The hull shader barrier used for this was broken by I/O normalization, since vocp is no longer exposed to the spirv backend. Restore this barrier by checking for vocp during normalization instead.
2023-07-16 21:34:04 -07:00
if (reg->type == VKD3DSPR_OUTCONTROLPOINT)
normaliser->use_vocp = true;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
/* We don't need to keep OUTCONTROLPOINT or PATCHCONST input declarations since their
* equivalents were declared earlier, but INCONTROLPOINT may be the first occurrence. */
if (reg->type == VKD3DSPR_OUTCONTROLPOINT || reg->type == VKD3DSPR_PATCHCONST)
vkd3d_shader_instruction_make_nop(ins);
else if (reg->type == VKD3DSPR_INCONTROLPOINT)
reg->type = VKD3DSPR_INPUT;
}
/* fall through */
case VKD3DSIH_DCL_INPUT_PS:
case VKD3DSIH_DCL_OUTPUT:
vkd3d-shader/ir: Simplify the control flow in shader_instruction_normalise_io_params().
2023-09-08 07:07:45 -07:00
if (!shader_dst_param_io_normalise(&ins->declaration.dst, true, normaliser))
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
break;
case VKD3DSIH_DCL_INPUT_SGV:
case VKD3DSIH_DCL_INPUT_SIV:
case VKD3DSIH_DCL_INPUT_PS_SGV:
case VKD3DSIH_DCL_INPUT_PS_SIV:
case VKD3DSIH_DCL_OUTPUT_SIV:
vkd3d-shader/ir: Simplify the control flow in shader_instruction_normalise_io_params().
2023-09-08 07:07:45 -07:00
if (!shader_dst_param_io_normalise(&ins->declaration.register_semantic.reg, true, normaliser))
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
break;
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
normaliser->phase = ins->handler_idx;
memset(normaliser->input_dcl_params, 0, sizeof(normaliser->input_dcl_params));
memset(normaliser->output_dcl_params, 0, sizeof(normaliser->output_dcl_params));
memset(normaliser->pc_dcl_params, 0, sizeof(normaliser->pc_dcl_params));
break;
default:
if (shader_instruction_is_dcl(ins))
break;
for (i = 0; i < ins->dst_count; ++i)
shader_dst_param_io_normalise((struct vkd3d_shader_dst_param *)&ins->dst[i], false, normaliser);
for (i = 0; i < ins->src_count; ++i)
shader_src_param_io_normalise((struct vkd3d_shader_src_param *)&ins->src[i], normaliser);
break;
}
}
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
static enum vkd3d_result shader_normalise_io_registers(struct vkd3d_shader_parser *parser)
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
struct io_normaliser normaliser = {parser->instructions};
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
struct vkd3d_shader_instruction *ins;
bool has_control_point_phase;
unsigned int i, j;
normaliser.phase = VKD3DSIH_INVALID;
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
normaliser.shader_type = parser->shader_version.type;
normaliser.input_signature = &parser->shader_desc.input_signature;
normaliser.output_signature = &parser->shader_desc.output_signature;
normaliser.patch_constant_signature = &parser->shader_desc.patch_constant_signature;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
for (i = 0, has_control_point_phase = false; i < parser->instructions.count; ++i)
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
ins = &parser->instructions.elements[i];
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
switch (ins->handler_idx)
{
case VKD3DSIH_DCL_OUTPUT_CONTROL_POINT_COUNT:
normaliser.output_control_point_count = ins->declaration.count;
break;
case VKD3DSIH_DCL_INDEX_RANGE:
io_normaliser_add_index_range(&normaliser, ins);
vkd3d_shader_instruction_make_nop(ins);
break;
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
has_control_point_phase = true;
/* fall through */
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
normaliser.phase = ins->handler_idx;
break;
default:
break;
}
}
if (normaliser.shader_type == VKD3D_SHADER_TYPE_HULL && !has_control_point_phase)
{
/* Inputs and outputs must match for the default phase, so merge ranges must match too. */
for (i = 0; i < MAX_REG_OUTPUT; ++i)
{
for (j = 0; j < VKD3D_VEC4_SIZE; ++j)
{
if (!normaliser.input_range_map[i][j] && normaliser.output_range_map[i][j])
normaliser.input_range_map[i][j] = normaliser.output_range_map[i][j];
else if (normaliser.input_range_map[i][j] && !normaliser.output_range_map[i][j])
normaliser.output_range_map[i][j] = normaliser.input_range_map[i][j];
else assert(normaliser.input_range_map[i][j] == normaliser.output_range_map[i][j]);
}
}
}
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
if (!shader_signature_merge(&parser->shader_desc.input_signature, normaliser.input_range_map, false)
|| !shader_signature_merge(&parser->shader_desc.output_signature, normaliser.output_range_map, false)
|| !shader_signature_merge(&parser->shader_desc.patch_constant_signature, normaliser.pc_range_map, true))
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
{
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
parser->instructions = normaliser.instructions;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
return VKD3D_ERROR_OUT_OF_MEMORY;
}
normaliser.phase = VKD3DSIH_INVALID;
for (i = 0; i < normaliser.instructions.count; ++i)
shader_instruction_normalise_io_params(&normaliser.instructions.elements[i], &normaliser);
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
parser->instructions = normaliser.instructions;
vkd3d-shader/ir: Check for vocp usage during IR normalization. The hull shader barrier used for this was broken by I/O normalization, since vocp is no longer exposed to the spirv backend. Restore this barrier by checking for vocp during normalization instead.
2023-07-16 21:34:04 -07:00
parser->shader_desc.use_vocp = normaliser.use_vocp;
vkd3d-shader/ir: Normalise signatures and input/output registers to the Shader Model 6 pattern. In Shader Model 6 each signature element can span a range of register indices, or 'rows', and system values do not share a register index with non-system values. Inputs and outputs are referenced by element index instead of register index. This patch merges multiple signature elements into a single element under the following conditions: - The register index in a load or store is specified dynamically by including a relative address parameter with a base register index. The dcl_index_range instruction is used to identify these. - A register declaration is split across multiple elements which declare different components of the register. - A patch constant function writes tessellation factors. These are an array in SPIR-V, but in SM 5.x each factor is declared as a separate register, and these are dynamically indexed by the fork/join instance id. Elimination of multiple fork/join phases converts the indices to constants, but merging the signature elements into a single arrayed element matches the SPIR-V output. All references to input/output register indices are converted to element indices. If a relative address is present, the element index is moved up a slot so it cannot be confused with a constant offset. Existing code only handles register index relative addressing for tessellation factors. This patch adds generic support for it.
2023-04-25 22:27:08 -07:00
return VKD3D_OK;
}
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
struct flat_constant_def
{
enum vkd3d_shader_d3dbc_constant_register set;
uint32_t index;
uint32_t value[4];
};
struct flat_constants_normaliser
{
struct vkd3d_shader_parser *parser;
struct flat_constant_def *defs;
size_t def_count, defs_capacity;
};
static bool get_flat_constant_register_type(const struct vkd3d_shader_register *reg,
enum vkd3d_shader_d3dbc_constant_register *set, uint32_t *index)
{
static const struct
{
enum vkd3d_shader_register_type type;
enum vkd3d_shader_d3dbc_constant_register set;
uint32_t offset;
}
regs[] =
{
{VKD3DSPR_CONST, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 0},
{VKD3DSPR_CONST2, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 2048},
{VKD3DSPR_CONST3, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 4096},
{VKD3DSPR_CONST4, VKD3D_SHADER_D3DBC_FLOAT_CONSTANT_REGISTER, 6144},
{VKD3DSPR_CONSTINT, VKD3D_SHADER_D3DBC_INT_CONSTANT_REGISTER, 0},
{VKD3DSPR_CONSTBOOL, VKD3D_SHADER_D3DBC_BOOL_CONSTANT_REGISTER, 0},
};
unsigned int i;
for (i = 0; i < ARRAY_SIZE(regs); ++i)
{
if (reg->type == regs[i].type)
{
if (reg->idx[0].rel_addr)
{
FIXME("Unhandled relative address.\n");
return false;
}
*set = regs[i].set;
*index = regs[i].offset + reg->idx[0].offset;
return true;
}
}
return false;
}
static void shader_register_normalise_flat_constants(struct vkd3d_shader_src_param *param,
const struct flat_constants_normaliser *normaliser)
{
enum vkd3d_shader_d3dbc_constant_register set;
uint32_t index;
size_t i, j;
if (!get_flat_constant_register_type(&param->reg, &set, &index))
return;
for (i = 0; i < normaliser->def_count; ++i)
{
if (normaliser->defs[i].set == set && normaliser->defs[i].index == index)
{
param->reg.type = VKD3DSPR_IMMCONST;
param->reg.idx_count = 0;
vkd3d-shader: Turn vkd3d_shader_register.immconst_type into vkd3d_shader_register.dimension.
2023-08-14 10:21:41 -07:00
param->reg.dimension = VSIR_DIMENSION_VEC4;
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
for (j = 0; j < 4; ++j)
param->reg.u.immconst_uint[j] = normaliser->defs[i].value[j];
return;
}
}
param->reg.type = VKD3DSPR_CONSTBUFFER;
param->reg.idx[0].offset = set; /* register ID */
param->reg.idx[1].offset = set; /* register index */
param->reg.idx[2].offset = index; /* buffer index */
param->reg.idx_count = 3;
}
static enum vkd3d_result instruction_array_normalise_flat_constants(struct vkd3d_shader_parser *parser)
{
struct flat_constants_normaliser normaliser = {.parser = parser};
unsigned int i, j;
for (i = 0; i < parser->instructions.count; ++i)
{
struct vkd3d_shader_instruction *ins = &parser->instructions.elements[i];
if (ins->handler_idx == VKD3DSIH_DEF || ins->handler_idx == VKD3DSIH_DEFI || ins->handler_idx == VKD3DSIH_DEFB)
{
struct flat_constant_def *def;
if (!vkd3d_array_reserve((void **)&normaliser.defs, &normaliser.defs_capacity,
normaliser.def_count + 1, sizeof(*normaliser.defs)))
{
vkd3d_free(normaliser.defs);
return VKD3D_ERROR_OUT_OF_MEMORY;
}
def = &normaliser.defs[normaliser.def_count++];
get_flat_constant_register_type((struct vkd3d_shader_register *)&ins->dst[0].reg, &def->set, &def->index);
for (j = 0; j < 4; ++j)
def->value[j] = ins->src[0].reg.u.immconst_uint[j];
vkd3d_shader_instruction_make_nop(ins);
}
else
{
for (j = 0; j < ins->src_count; ++j)
shader_register_normalise_flat_constants((struct vkd3d_shader_src_param *)&ins->src[j], &normaliser);
}
}
vkd3d_free(normaliser.defs);
return VKD3D_OK;
}
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
static void remove_dead_code(struct vkd3d_shader_parser *parser)
{
size_t i, depth = 0;
bool dead = false;
for (i = 0; i < parser->instructions.count; ++i)
{
struct vkd3d_shader_instruction *ins = &parser->instructions.elements[i];
switch (ins->handler_idx)
{
case VKD3DSIH_IF:
case VKD3DSIH_LOOP:
case VKD3DSIH_SWITCH:
if (dead)
{
vkd3d_shader_instruction_make_nop(ins);
++depth;
}
break;
case VKD3DSIH_ENDIF:
case VKD3DSIH_ENDLOOP:
case VKD3DSIH_ENDSWITCH:
case VKD3DSIH_ELSE:
if (dead)
{
if (depth > 0)
{
if (ins->handler_idx != VKD3DSIH_ELSE)
--depth;
vkd3d-shader/ir: Check the handler before changing it to NOP in remove_dead_code().
2023-11-08 20:07:03 -08:00
vkd3d_shader_instruction_make_nop(ins);
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
}
else
{
dead = false;
}
}
break;
/* `depth' is counted with respect to where the dead code
* segment began. So it starts at zero and it signals the
* termination of the dead code segment when it would
* become negative. */
case VKD3DSIH_BREAK:
case VKD3DSIH_RET:
case VKD3DSIH_CONTINUE:
if (dead)
{
vkd3d_shader_instruction_make_nop(ins);
}
else
{
dead = true;
depth = 0;
}
break;
/* If `case' or `default' appears at zero depth, it means
* that they are a possible target for the corresponding
* switch, so the code is live again. */
case VKD3DSIH_CASE:
case VKD3DSIH_DEFAULT:
if (dead)
{
if (depth == 0)
dead = false;
else
vkd3d_shader_instruction_make_nop(ins);
}
break;
/* Phase instructions can only appear in hull shaders and
* outside of any block. When a phase returns, control is
* moved to the following phase, so they make code live
* again. */
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
dead = false;
break;
default:
if (dead)
vkd3d_shader_instruction_make_nop(ins);
break;
}
}
}
vkd3d-shader/ir: Translate TEX instructions to SAMPLE.
2023-08-11 14:46:03 -07:00
static enum vkd3d_result normalise_combined_samplers(struct vkd3d_shader_parser *parser)
{
unsigned int i;
for (i = 0; i < parser->instructions.count; ++i)
{
struct vkd3d_shader_instruction *ins = &parser->instructions.elements[i];
struct vkd3d_shader_src_param *srcs;
switch (ins->handler_idx)
{
case VKD3DSIH_TEX:
if (!(srcs = shader_src_param_allocator_get(&parser->instructions.src_params, 3)))
return VKD3D_ERROR_OUT_OF_MEMORY;
memset(srcs, 0, sizeof(*srcs) * 3);
ins->handler_idx = VKD3DSIH_SAMPLE;
srcs[0] = ins->src[0];
srcs[1].reg.type = VKD3DSPR_RESOURCE;
srcs[1].reg.idx[0] = ins->src[1].reg.idx[0];
srcs[1].reg.idx[1] = ins->src[1].reg.idx[0];
srcs[1].reg.idx_count = 2;
srcs[1].reg.data_type = VKD3D_DATA_RESOURCE;
srcs[1].swizzle = VKD3D_SHADER_NO_SWIZZLE;
srcs[2].reg.type = VKD3DSPR_SAMPLER;
srcs[2].reg.idx[0] = ins->src[1].reg.idx[0];
srcs[2].reg.idx[1] = ins->src[1].reg.idx[0];
srcs[2].reg.idx_count = 2;
srcs[2].reg.data_type = VKD3D_DATA_SAMPLER;
ins->src = srcs;
ins->src_count = 3;
break;
case VKD3DSIH_TEXBEM:
case VKD3DSIH_TEXBEML:
case VKD3DSIH_TEXCOORD:
case VKD3DSIH_TEXDEPTH:
case VKD3DSIH_TEXDP3:
case VKD3DSIH_TEXDP3TEX:
case VKD3DSIH_TEXLDD:
case VKD3DSIH_TEXLDL:
case VKD3DSIH_TEXM3x2PAD:
case VKD3DSIH_TEXM3x2TEX:
case VKD3DSIH_TEXM3x3DIFF:
case VKD3DSIH_TEXM3x3PAD:
case VKD3DSIH_TEXM3x3SPEC:
case VKD3DSIH_TEXM3x3TEX:
case VKD3DSIH_TEXM3x3VSPEC:
case VKD3DSIH_TEXREG2AR:
case VKD3DSIH_TEXREG2GB:
case VKD3DSIH_TEXREG2RGB:
vkd3d_shader_parser_error(parser, VKD3D_SHADER_ERROR_VSIR_NOT_IMPLEMENTED,
"Aborting due to not yet implemented feature: "
"Combined sampler instruction %#x.", ins->handler_idx);
return VKD3D_ERROR_NOT_IMPLEMENTED;
default:
break;
}
}
return VKD3D_OK;
}
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
enum vkd3d_result vkd3d_shader_normalise(struct vkd3d_shader_parser *parser,
const struct vkd3d_shader_compile_info *compile_info)
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
{
struct vkd3d_shader_instruction_array *instructions = &parser->instructions;
enum vkd3d_result result = VKD3D_OK;
vkd3d-shader/spirv: Do not normalise Shader Model 6 shaders.
2023-06-02 07:23:49 -07:00
if (parser->shader_desc.is_dxil)
return result;
vkd3d-shader: Implement remapping shader output registers to match the next shader's semantics.
2023-07-20 19:52:25 -07:00
if (parser->shader_version.type != VKD3D_SHADER_TYPE_PIXEL
&& (result = remap_output_signature(parser, compile_info)) < 0)
return result;
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
if (parser->shader_version.type == VKD3D_SHADER_TYPE_HULL
&& (result = instruction_array_flatten_hull_shader_phases(instructions)) >= 0)
{
result = instruction_array_normalise_hull_shader_control_point_io(instructions,
&parser->shader_desc.input_signature);
}
if (result >= 0)
vkd3d-shader/ir: Pass a vkd3d_shader_parser to instruction_array_normalise_io_registers().
2023-07-16 21:27:52 -07:00
result = shader_normalise_io_registers(parser);
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
vkd3d-shader/ir: Normalise sm1-style constants.
2023-07-09 15:46:04 -07:00
if (result >= 0)
result = instruction_array_normalise_flat_constants(parser);
vkd3d-shader/ir: Remove dead code during normalisation. The SPIR-V backend generates invalid SPIR-V code when VSIR has dead code (except for NOPs).
2023-09-20 13:10:39 -07:00
if (result >= 0)
remove_dead_code(parser);
vkd3d-shader/ir: Translate TEX instructions to SAMPLE.
2023-08-11 14:46:03 -07:00
if (result >= 0)
result = normalise_combined_samplers(parser);
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
if (result >= 0 && TRACE_ON())
vkd3d_shader_trace(instructions, &parser->shader_version);
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
if (result >= 0 && !parser->failed)
vsir_validate(parser);
if (result >= 0 && parser->failed)
result = VKD3D_ERROR_INVALID_SHADER;
vkd3d-shader/ir: Move normalization code from spirv.c to ir.c. It is not spirv-specific and will (presumably) be used for GLSL as well.
2023-07-02 18:23:07 -07:00
return result;
}
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
struct validation_context
{
struct vkd3d_shader_parser *parser;
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
size_t instruction_idx;
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
bool dcl_temps_found;
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
unsigned int temp_count;
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
enum vkd3d_shader_opcode phase;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
enum vkd3d_shader_opcode *blocks;
size_t depth;
size_t blocks_capacity;
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
};
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
static void VKD3D_PRINTF_FUNC(3, 4) validator_error(struct validation_context *ctx,
enum vkd3d_shader_error error, const char *format, ...)
{
struct vkd3d_string_buffer buf;
va_list args;
vkd3d_string_buffer_init(&buf);
va_start(args, format);
vkd3d_string_buffer_vprintf(&buf, format, args);
va_end(args);
vkd3d_shader_parser_error(ctx->parser, error, "instruction %zu: %s", ctx->instruction_idx + 1, buf.buffer);
vkd3d-shader/ir: Emit an ERR() on validation errors.
2023-11-06 04:15:23 -08:00
ERR("VSIR validation error: instruction %zu: %s\n", ctx->instruction_idx + 1, buf.buffer);
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
vkd3d_string_buffer_cleanup(&buf);
}
vkd3d-shader/ir: Validate register indices.
2023-11-08 14:10:06 -08:00
static void vsir_validate_src_param(struct validation_context *ctx,
const struct vkd3d_shader_src_param *src);
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
static void vsir_validate_register(struct validation_context *ctx,
const struct vkd3d_shader_register *reg)
{
vkd3d-shader/ir: Validate register indices.
2023-11-08 14:10:06 -08:00
unsigned int i, temp_count = ctx->temp_count;
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
/* SM1-3 shaders do not include a DCL_TEMPS instruction. */
if (ctx->parser->shader_version.major <= 3)
temp_count = ctx->parser->shader_desc.temp_count;
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
if (reg->type >= VKD3DSPR_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_REGISTER_TYPE, "Invalid register type %#x.",
reg->type);
vkd3d-shader/ir: Validate the register precision.
2023-10-24 17:37:40 -07:00
if (reg->precision >= VKD3D_SHADER_REGISTER_PRECISION_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_PRECISION, "Invalid register precision %#x.",
reg->precision);
vkd3d-shader/ir: Validate the register data type.
2023-10-24 17:41:09 -07:00
if (reg->data_type >= VKD3D_DATA_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DATA_TYPE, "Invalid register data type %#x.",
reg->data_type);
vkd3d-shader/ir: Validate the register dimension.
2023-10-24 17:43:31 -07:00
if (reg->dimension >= VSIR_DIMENSION_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DIMENSION, "Invalid register dimension %#x.",
reg->dimension);
vkd3d-shader/ir: Validate the register index count.
2023-10-24 17:46:07 -07:00
if (reg->idx_count > ARRAY_SIZE(reg->idx))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid register index count %u.",
reg->idx_count);
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
vkd3d-shader/ir: Validate register indices.
2023-11-08 14:10:06 -08:00
for (i = 0; i < min(reg->idx_count, ARRAY_SIZE(reg->idx)); ++i)
{
const struct vkd3d_shader_src_param *param = reg->idx[i].rel_addr;
if (reg->idx[i].rel_addr)
vsir_validate_src_param(ctx, param);
}
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
switch (reg->type)
{
case VKD3DSPR_TEMP:
if (reg->idx_count != 1)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a TEMP register.",
reg->idx_count);
if (reg->idx_count >= 1 && reg->idx[0].rel_addr)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "Non-NULL relative address for a TEMP register.");
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
if (reg->idx_count >= 1 && reg->idx[0].offset >= temp_count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX, "TEMP register index %u exceeds the maximum count %u.",
reg->idx[0].offset, temp_count);
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
break;
vkd3d-shader/ir: Validate index count for NULL registers.
2023-11-08 14:12:30 -08:00
case VKD3DSPR_NULL:
if (reg->idx_count != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a NULL register.",
reg->idx_count);
break;
vkd3d-shader/ir: Validate index count for IMMCONST registers.
2023-11-08 14:17:05 -08:00
case VKD3DSPR_IMMCONST:
if (reg->idx_count != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a IMMCONST register.",
reg->idx_count);
break;
vkd3d-shader/ir: Validate index count for IMMCONST64 registers.
2023-11-08 14:17:39 -08:00
case VKD3DSPR_IMMCONST64:
if (reg->idx_count != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INDEX_COUNT, "Invalid index count %u for a IMMCONST64 register.",
reg->idx_count);
break;
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
default:
break;
}
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
}
static void vsir_validate_dst_param(struct validation_context *ctx,
const struct vkd3d_shader_dst_param *dst)
{
vsir_validate_register(ctx, &dst->reg);
vkd3d-shader/ir: Validate destination parameters.
2023-08-29 13:17:28 -07:00
if (dst->write_mask & ~VKD3DSP_WRITEMASK_ALL)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_WRITE_MASK, "Destination has invalid write mask %#x.",
dst->write_mask);
if (dst->modifiers & ~VKD3DSPDM_MASK)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_MODIFIERS, "Destination has invalid modifiers %#x.",
dst->modifiers);
switch (dst->shift)
{
case 0:
case 1:
case 2:
case 3:
case 13:
case 14:
case 15:
break;
default:
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SHIFT, "Destination has invalid shift %#x.",
dst->shift);
}
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
}
static void vsir_validate_src_param(struct validation_context *ctx,
const struct vkd3d_shader_src_param *src)
{
vsir_validate_register(ctx, &src->reg);
vkd3d-shader/ir: Validate source parameters.
2023-08-29 13:23:02 -07:00
if (src->swizzle & ~0x03030303u)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SWIZZLE, "Source has invalid swizzle %#x.",
src->swizzle);
if (src->modifiers >= VKD3DSPSM_COUNT)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_MODIFIERS, "Source has invalid modifiers %#x.",
src->modifiers);
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
}
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
static void vsir_validate_dst_count(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction, unsigned int count)
{
if (instruction->dst_count != count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DEST_COUNT,
"Invalid destination count %u for an instruction of type %#x, expected %u.",
instruction->dst_count, instruction->handler_idx, count);
}
static void vsir_validate_src_count(struct validation_context *ctx,
const struct vkd3d_shader_instruction *instruction, unsigned int count)
{
if (instruction->src_count != count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_SOURCE_COUNT,
"Invalid source count %u for an instruction of type %#x, expected %u.",
instruction->src_count, instruction->handler_idx, count);
}
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
static void vsir_validate_instruction(struct validation_context *ctx)
{
const struct vkd3d_shader_instruction *instruction = &ctx->parser->instructions.elements[ctx->instruction_idx];
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
size_t i;
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
ctx->parser->location = instruction->location;
vkd3d-shader/ir: Validate register types.
2023-08-29 12:58:31 -07:00
for (i = 0; i < instruction->dst_count; ++i)
vsir_validate_dst_param(ctx, &instruction->dst[i]);
for (i = 0; i < instruction->src_count; ++i)
vsir_validate_src_param(ctx, &instruction->src[i]);
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
if (instruction->handler_idx >= VKD3DSIH_INVALID)
{
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_HANDLER, "Invalid instruction handler %#x.",
instruction->handler_idx);
}
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
switch (instruction->handler_idx)
{
case VKD3DSIH_HS_DECLS:
case VKD3DSIH_HS_CONTROL_POINT_PHASE:
case VKD3DSIH_HS_FORK_PHASE:
case VKD3DSIH_HS_JOIN_PHASE:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->parser->shader_version.type != VKD3D_SHADER_TYPE_HULL)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_HANDLER, "Phase instruction %#x is only valid in a hull shader.",
instruction->handler_idx);
if (ctx->depth != 0)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INSTRUCTION_NESTING, "Phase instruction %#x must appear to top level.",
instruction->handler_idx);
ctx->phase = instruction->handler_idx;
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
ctx->dcl_temps_found = false;
ctx->temp_count = 0;
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
return;
default:
break;
}
if (ctx->parser->shader_version.type == VKD3D_SHADER_TYPE_HULL &&
ctx->phase == VKD3DSIH_INVALID)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_HANDLER, "Instruction %#x appear before any phase instruction in a hull shader.",
instruction->handler_idx);
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
switch (instruction->handler_idx)
{
case VKD3DSIH_DCL_TEMPS:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
if (ctx->dcl_temps_found)
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_DUPLICATE_DCL_TEMPS, "Duplicate DCL_TEMPS instruction.");
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
if (instruction->declaration.count > ctx->parser->shader_desc.temp_count)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_DCL_TEMPS, "Invalid DCL_TEMPS count %u, expected at most %u.",
vkd3d-shader/ir: Validate the index of a TEMP register.
2023-10-24 17:55:37 -07:00
instruction->declaration.count, ctx->parser->shader_desc.temp_count);
vkd3d-shader/ir: Validate the TEMP register indices in each HS phase.
2023-11-07 14:21:11 -08:00
ctx->dcl_temps_found = true;
ctx->temp_count = instruction->declaration.count;
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
break;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
case VKD3DSIH_IF:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 1);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
vkd3d-shader/ir: Validate IFC instructions.
2023-11-16 13:32:13 -08:00
case VKD3DSIH_IFC:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 2);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = VKD3DSIH_IF;
break;
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
case VKD3DSIH_ELSE:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_IF)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INSTRUCTION_NESTING, "ELSE instruction doesn't terminate IF block.");
else
ctx->blocks[ctx->depth - 1] = instruction->handler_idx;
break;
case VKD3DSIH_ENDIF:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || (ctx->blocks[ctx->depth - 1] != VKD3DSIH_IF && ctx->blocks[ctx->depth - 1] != VKD3DSIH_ELSE))
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INSTRUCTION_NESTING, "ENDIF instruction doesn't terminate IF/ELSE block.");
else
--ctx->depth;
break;
vkd3d-shader/ir: Check that LOOP blocks are correctly nested.
2023-11-06 04:54:07 -08:00
case VKD3DSIH_LOOP:
vsir_validate_dst_count(ctx, instruction, 0);
vkd3d-shader/ir: Expect two sources for LOOP in SM1-3.
2023-11-16 13:30:12 -08:00
vsir_validate_src_count(ctx, instruction, ctx->parser->shader_version.major <= 3 ? 2 : 0);
vkd3d-shader/ir: Check that LOOP blocks are correctly nested.
2023-11-06 04:54:07 -08:00
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
case VKD3DSIH_ENDLOOP:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_LOOP)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INSTRUCTION_NESTING, "ENDLOOP instruction doesn't terminate LOOP block.");
else
--ctx->depth;
break;
vkd3d-shader/ir: Check that REP blocks are correctly nested.
2023-11-06 04:56:38 -08:00
case VKD3DSIH_REP:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 1);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
case VKD3DSIH_ENDREP:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_REP)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INSTRUCTION_NESTING, "ENDREP instruction doesn't terminate REP block.");
else
--ctx->depth;
break;
vkd3d-shader/ir: Check that SWITCH blocks are correctly nested.
2023-11-06 04:57:25 -08:00
case VKD3DSIH_SWITCH:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 1);
if (!vkd3d_array_reserve((void **)&ctx->blocks, &ctx->blocks_capacity, ctx->depth + 1, sizeof(*ctx->blocks)))
return;
ctx->blocks[ctx->depth++] = instruction->handler_idx;
break;
case VKD3DSIH_ENDSWITCH:
vsir_validate_dst_count(ctx, instruction, 0);
vsir_validate_src_count(ctx, instruction, 0);
if (ctx->depth == 0 || ctx->blocks[ctx->depth - 1] != VKD3DSIH_SWITCH)
validator_error(ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INSTRUCTION_NESTING, "ENDSWITCH instruction doesn't terminate SWITCH block.");
else
--ctx->depth;
break;
vkd3d-shader/ir: Validate the DCL_TEMPS instruction.
2023-10-24 18:08:00 -07:00
default:
break;
}
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
}
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
void vsir_validate(struct vkd3d_shader_parser *parser)
{
vkd3d-shader/ir: Keep track of hull shader phases.
2023-11-06 14:11:03 -08:00
struct validation_context ctx =
{
.parser = parser,
.phase = VKD3DSIH_INVALID,
};
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
if (!(parser->config_flags & VKD3D_SHADER_CONFIG_FLAG_FORCE_VALIDATION))
return;
vkd3d-shader/ir: Validate instruction handlers.
2023-08-29 12:35:01 -07:00
for (ctx.instruction_idx = 0; ctx.instruction_idx < parser->instructions.count; ++ctx.instruction_idx)
vsir_validate_instruction(&ctx);
vkd3d-shader/ir: Check that IF blocks are correctly nested.
2023-11-06 04:47:34 -08:00
if (ctx.depth != 0)
validator_error(&ctx, VKD3D_SHADER_ERROR_VSIR_INVALID_INSTRUCTION_NESTING, "%zu nested blocks were not closed.", ctx.depth);
free(ctx.blocks);
vkd3d-shader/ir: Introduce a boilerplate to validate the generated IR. For the moment the validator is trivial, it never fails. Checks will be added incrementally.
2023-08-29 12:20:35 -07:00
}
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