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412 lines
17 KiB
C++
412 lines
17 KiB
C++
/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
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/* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is [Open Source Virtual Machine].
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*
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* The Initial Developer of the Original Code is
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* Adobe System Incorporated.
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* Portions created by the Initial Developer are Copyright (C) 2004-2007
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Adobe AS3 Team
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either the GNU General Public License Version 2 or later (the "GPL"), or
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* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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* in which case the provisions of the GPL or the LGPL are applicable instead
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* of those above. If you wish to allow use of your version of this file only
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* under the terms of either the GPL or the LGPL, and not to allow others to
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* use your version of this file under the terms of the MPL, indicate your
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* decision by deleting the provisions above and replace them with the notice
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* and other provisions required by the GPL or the LGPL. If you do not delete
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* the provisions above, a recipient may use your version of this file under
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* the terms of any one of the MPL, the GPL or the LGPL.
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef __nanojit_Assembler__
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#define __nanojit_Assembler__
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namespace nanojit
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{
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/**
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* Some notes on this Assembler (Emitter).
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*
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* The class RegAlloc is essentially the register allocator from MIR
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*
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* The Assembler class parses the LIR instructions starting at any point and converts
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* them to machine code. It does the translation using expression trees which are simply
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* LIR instructions in the stream that have side-effects. Any other instruction in the
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* stream is simply ignored.
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* This approach is interesting in that dead code elimination occurs for 'free', strength
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* reduction occurs fairly naturally, along with some other optimizations.
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*
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* A negative is that we require state as we 'push' and 'pop' nodes along the tree.
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* Also, this is most easily performed using recursion which may not be desirable in
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* the mobile environment.
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*
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*/
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#define STACK_GRANULARITY sizeof(void *)
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// Basics:
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// - 'entry' records the state of the native machine stack at particular
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// points during assembly. Each entry represents four bytes.
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//
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// - Parts of the stack can be allocated by LIR_ialloc, in which case each
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// slot covered by the allocation contains a pointer to the LIR_ialloc
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// LIns.
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//
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// - The stack also holds spilled values, in which case each slot holding
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// a spilled value (one slot for 32-bit values, two slots for 64-bit
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// values) contains a pointer to the instruction defining the spilled
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// value.
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//
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// - Each LIns has a Reservation which includes a stack index, 'arIndex'.
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// Combined with AR, it provides a two-way mapping between stack slots
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// and LIR instructions.
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//
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// - Invariant: the two-way mapping between active stack slots and their
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// defining/allocating instructions must hold in both directions and be
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// unambiguous. More specifically:
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//
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// * An LIns can appear in at most one contiguous sequence of slots in
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// AR, and the length of that sequence depends on the opcode (1 slot
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// for instructions producing 32-bit values, 2 slots for instructions
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// producing 64-bit values, N slots for LIR_ialloc).
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//
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// * An LIns named by 'entry[i]' must have an in-use Reservation with
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// arIndex==i (or an 'i' indexing the start of the same contiguous
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// sequence that 'entry[i]' belongs to).
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//
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// * And vice versa: an LIns with an in-use Reservation with arIndex==i
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// must be named by 'entry[i]'.
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//
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// * If an LIns's Reservation names has arIndex==0 then LIns should not
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// be in 'entry[]'.
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//
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struct AR
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{
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LIns* entry[ NJ_MAX_STACK_ENTRY ]; /* maps to 4B contiguous locations relative to the frame pointer */
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uint32_t tos; /* current top of stack entry */
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uint32_t lowwatermark; /* we pre-allocate entries from 0 upto this index-1; so dynamic entries are added above this index */
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};
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#ifndef AVMPLUS_ALIGN16
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#ifdef AVMPLUS_WIN32
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#define AVMPLUS_ALIGN16(type) __declspec(align(16)) type
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#else
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#define AVMPLUS_ALIGN16(type) type __attribute__ ((aligned (16)))
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#endif
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#endif
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struct Stats
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{
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counter_define(steals;)
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counter_define(remats;)
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counter_define(spills;)
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counter_define(native;)
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counter_define(exitnative;)
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int32_t pages;
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NIns* codeStart;
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NIns* codeExitStart;
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DECLARE_PLATFORM_STATS()
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#ifdef __GNUC__
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// inexplicably, gnuc gives padding/alignment warnings without this. pacify it.
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bool pad[4];
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#endif
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};
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// error codes
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enum AssmError
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{
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None = 0
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,StackFull
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,UnknownBranch
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};
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typedef SeqBuilder<NIns*> NInsList;
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typedef HashMap<NIns*, LIns*> NInsMap;
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#ifdef VTUNE
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class avmplus::CodegenLIR;
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#endif
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class LabelState
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{
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public:
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RegAlloc regs;
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NIns *addr;
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LabelState(NIns *a, RegAlloc &r) : regs(r), addr(a)
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{}
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};
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class LabelStateMap
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{
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Allocator& alloc;
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HashMap<LIns*, LabelState*> labels;
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public:
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LabelStateMap(Allocator& alloc) : alloc(alloc), labels(alloc)
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{}
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void clear() { labels.clear(); }
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void add(LIns *label, NIns *addr, RegAlloc ®s);
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LabelState *get(LIns *);
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};
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typedef SeqBuilder<char*> StringList;
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/** map tracking the register allocation state at each bailout point
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* (represented by SideExit*) in a trace fragment. */
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typedef HashMap<SideExit*, RegAlloc*> RegAllocMap;
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/**
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* Information about the activation record for the method is built up
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* as we generate machine code. As part of the prologue, we issue
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* a stack adjustment instruction and then later patch the adjustment
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* value. Temporary values can be placed into the AR as method calls
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* are issued. Also LIR_alloc instructions will consume space.
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*/
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class Assembler
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{
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friend class VerboseBlockReader;
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public:
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#ifdef NJ_VERBOSE
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static char outline[8192];
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static char outlineEOL[512]; // string to be added to the end of the line
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static char* outputAlign(char* s, int col);
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void outputForEOL(const char* format, ...);
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void output(const char* s);
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void outputf(const char* format, ...);
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void output_asm(const char* s);
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bool outputAddr, vpad[3]; // if outputAddr=true then next asm instr. will include address in output
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void printActivationState(const char* what);
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StringList* _outputCache;
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// Log controller object. Contains what-stuff-should-we-print
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// bits, and a sink function for debug printing
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LogControl* _logc;
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#endif // NJ_VERBOSE
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#ifdef VTUNE
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avmplus::CodegenLIR *cgen;
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#endif
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Assembler(CodeAlloc& codeAlloc, Allocator& dataAlloc, Allocator& alloc, AvmCore* core, LogControl* logc);
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void endAssembly(Fragment* frag);
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void assemble(Fragment* frag, LirFilter* reader);
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void beginAssembly(Fragment *frag);
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void releaseRegisters();
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void patch(GuardRecord *lr);
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void patch(SideExit *exit);
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#ifdef NANOJIT_IA32
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void patch(SideExit *exit, SwitchInfo* si);
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#endif
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AssmError error() { return _err; }
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void setError(AssmError e) { _err = e; }
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void reset();
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debug_only ( void pageValidate(); )
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// support calling out from a fragment ; used to debug the jit
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debug_only( void resourceConsistencyCheck(); )
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debug_only( void registerConsistencyCheck(); )
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Stats _stats;
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CodeList* codeList; // finished blocks of code.
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private:
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void gen(LirFilter* toCompile);
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NIns* genPrologue();
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NIns* genEpilogue();
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uint32_t arReserve(LIns* l);
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void arFree(uint32_t idx);
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void arReset();
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Register registerAlloc(LIns* ins, RegisterMask allow);
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Register registerAllocTmp(RegisterMask allow);
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void registerResetAll();
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void evictAllActiveRegs();
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void evictSomeActiveRegs(RegisterMask regs);
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void evictScratchRegs();
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void intersectRegisterState(RegAlloc& saved);
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void unionRegisterState(RegAlloc& saved);
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void assignSaved(RegAlloc &saved, RegisterMask skip);
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LInsp findVictim(RegisterMask allow);
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Register getBaseReg(LOpcode op, LIns *i, int &d, RegisterMask allow);
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int findMemFor(LIns* i);
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Register findRegFor(LIns* i, RegisterMask allow);
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void findRegFor2(RegisterMask allow, LIns* ia, Reservation* &resva, LIns *ib, Reservation* &resvb);
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void findRegFor2b(RegisterMask allow, LIns* ia, Register &ra, LIns *ib, Register &rb);
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Register findSpecificRegFor(LIns* i, Register r);
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Register findSpecificRegForUnallocated(LIns* i, Register r);
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Register prepResultReg(LIns *i, RegisterMask allow);
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void freeRsrcOf(LIns *i, bool pop);
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void evictIfActive(Register r);
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void evict(Register r, LIns* vic);
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RegisterMask hint(LIns*i, RegisterMask allow);
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void codeAlloc(NIns *&start, NIns *&end, NIns *&eip
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verbose_only(, size_t &nBytes));
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bool canRemat(LIns*);
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bool isKnownReg(Register r) {
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return r != UnknownReg;
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}
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Reservation* getresv(LIns *x) {
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Reservation* r = x->resv();
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return r->used ? r : 0;
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}
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Allocator& alloc; // for items with same lifetime as this Assembler
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CodeAlloc& _codeAlloc; // for code we generate
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Allocator& _dataAlloc; // for data used by generated code
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Fragment* _thisfrag;
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RegAllocMap _branchStateMap;
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NInsMap _patches;
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LabelStateMap _labels;
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// We generate code into two places: normal code chunks, and exit
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// code chunks (for exit stubs). We use a hack to avoid having to
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// parameterise the code that does the generating -- we let that
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// code assume that it's always generating into a normal code
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// chunk (most of the time it is), and when we instead need to
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// generate into an exit code chunk, we set _inExit to true and
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// temporarily swap all the code/exit variables below (using
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// swapCodeChunks()). Afterwards we swap them all back and set
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// _inExit to false again.
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bool _inExit, vpad2[3];
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NIns *codeStart, *codeEnd; // current normal code chunk
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NIns *exitStart, *exitEnd; // current exit code chunk
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NIns* _nIns; // current instruction in current normal code chunk
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NIns* _nExitIns; // current instruction in current exit code chunk
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#ifdef NJ_VERBOSE
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public:
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size_t codeBytes; // bytes allocated in normal code chunks
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size_t exitBytes; // bytes allocated in exit code chunks
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#endif
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private:
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#define SWAP(t, a, b) do { t tmp = a; a = b; b = tmp; } while (0)
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void swapCodeChunks();
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NIns* _epilogue;
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AssmError _err; // 0 = means assemble() appears ok, otherwise it failed
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#if PEDANTIC
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NIns* pedanticTop;
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#endif
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AR _activation;
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RegAlloc _allocator;
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verbose_only( void asm_inc_m32(uint32_t*); )
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void asm_mmq(Register rd, int dd, Register rs, int ds);
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NIns* asm_exit(LInsp guard);
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NIns* asm_leave_trace(LInsp guard);
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void asm_qjoin(LIns *ins);
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void asm_store32(LIns *val, int d, LIns *base);
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void asm_store64(LIns *val, int d, LIns *base);
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void asm_restore(LInsp, Reservation*, Register);
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void asm_load(int d, Register r);
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void asm_spilli(LInsp i, bool pop);
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void asm_spill(Register rr, int d, bool pop, bool quad);
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void asm_load64(LInsp i);
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void asm_ret(LInsp p);
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void asm_quad(LInsp i);
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void asm_fcond(LInsp i);
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void asm_cond(LInsp i);
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void asm_arith(LInsp i);
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void asm_neg_not(LInsp i);
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void asm_ld(LInsp i);
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void asm_cmov(LInsp i);
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void asm_param(LInsp i);
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void asm_int(LInsp i);
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void asm_qlo(LInsp i);
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void asm_qhi(LInsp i);
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void asm_fneg(LInsp ins);
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void asm_fop(LInsp ins);
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void asm_i2f(LInsp ins);
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void asm_u2f(LInsp ins);
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void asm_promote(LIns *ins);
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Register asm_prep_fcall(Reservation *rR, LInsp ins);
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void asm_nongp_copy(Register r, Register s);
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void asm_call(LInsp);
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Register asm_binop_rhs_reg(LInsp ins);
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NIns* asm_branch(bool branchOnFalse, LInsp cond, NIns* targ);
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void asm_switch(LIns* ins, NIns* target);
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void asm_jtbl(LIns* ins, NIns** table);
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void emitJumpTable(SwitchInfo* si, NIns* target);
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void assignSavedRegs();
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void reserveSavedRegs();
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void assignParamRegs();
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void handleLoopCarriedExprs(InsList& pending_lives);
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// platform specific implementation (see NativeXXX.cpp file)
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void nInit(AvmCore *);
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void nBeginAssembly();
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Register nRegisterAllocFromSet(RegisterMask set);
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void nRegisterResetAll(RegAlloc& a);
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static void nPatchBranch(NIns* branch, NIns* location);
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void nFragExit(LIns* guard);
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// platform specific methods
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public:
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const static Register savedRegs[NumSavedRegs];
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DECLARE_PLATFORM_ASSEMBLER()
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private:
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#ifdef NANOJIT_IA32
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debug_only( int32_t _fpuStkDepth; )
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debug_only( int32_t _sv_fpuStkDepth; )
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// since we generate backwards the depth is negative
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inline void fpu_push() {
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debug_only( ++_fpuStkDepth; /*char foo[8]= "FPUSTK0"; foo[6]-=_fpuStkDepth; output_asm(foo);*/ NanoAssert(_fpuStkDepth<=0); )
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}
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inline void fpu_pop() {
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debug_only( --_fpuStkDepth; /*char foo[8]= "FPUSTK0"; foo[6]-=_fpuStkDepth; output_asm(foo);*/ NanoAssert(_fpuStkDepth<=0); )
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}
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#endif
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avmplus::Config &config;
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};
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inline int32_t disp(Reservation* r)
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{
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// even on 64bit cpu's, we allocate stack area in 4byte chunks
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return stack_direction(4 * int32_t(r->arIndex));
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}
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inline int32_t disp(LIns* ins)
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{
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// even on 64bit cpu's, we allocate stack area in 4byte chunks
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return stack_direction(4 * int32_t(ins->getArIndex()));
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}
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}
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#endif // __nanojit_Assembler__
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