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716 lines
30 KiB
C++
716 lines
30 KiB
C++
/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: nil; tab-width: 4 -*- */
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/* vi: set ts=4 sw=4 expandtab: (add to ~/.vimrc: set modeline modelines=5) */
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is [Open Source Virtual Machine].
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*
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* The Initial Developer of the Original Code is
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* MIPS Technologies Inc
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* Portions created by the Initial Developer are Copyright (C) 2009
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Chris Dearman <chris@mips.com>
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either the GNU General Public License Version 2 or later (the "GPL"), or
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* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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* in which case the provisions of the GPL or the LGPL are applicable instead
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* of those above. If you wish to allow use of your version of this file only
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* under the terms of either the GPL or the LGPL, and not to allow others to
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* use your version of this file under the terms of the MPL, indicate your
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* decision by deleting the provisions above and replace them with the notice
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* and other provisions required by the GPL or the LGPL. If you do not delete
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* the provisions above, a recipient may use your version of this file under
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* the terms of any one of the MPL, the GPL or the LGPL.
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef __nanojit_NativeMIPS__
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#define __nanojit_NativeMIPS__
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#include "../vprof/vprof.h"
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#ifdef PERFM
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#define DOPROF
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#endif
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#define count_instr() _nvprof("mips", 1)
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#define count_mov() do { _nvprof("mips-mov", 1); count_instr(); } while (0)
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#define count_jmp() do { _nvprof("mips-jmp", 1); count_instr(); } while (0)
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#define count_prolog() do { _nvprof("mips-prolog", 1); count_instr(); } while (0)
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#define count_alu() do { _nvprof("mips-alu", 1); count_instr(); } while (0)
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#define count_misc() do { _nvprof("mips-misc", 1); count_instr(); } while (0)
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#define count_fpu() do { _nvprof("mips-fpu", 1); count_instr(); } while (0)
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#define count_br() do { _nvprof("mips-br", 1); count_instr(); } while (0)
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namespace nanojit
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{
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// Req: NJ_MAX_STACK_ENTRY is number of instructions to hold in LIR stack
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#if 0
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// FIXME: Inconsistent use in signed/unsigned expressions makes this generate errors
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static const uint32_t NJ_MAX_STACK_ENTRY = 4096;
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#else
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#define NJ_MAX_STACK_ENTRY 4096
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#endif
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static const int NJ_ALIGN_STACK = 8;
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typedef uint32_t NIns; // REQ: Instruction count
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typedef uint64_t RegisterMask; // REQ: Large enough to hold LastRegNum-FirstRegNum bits
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#define _rmask_(r) (1LL<<(r))
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typedef uint32_t Register; // REQ: Register identifiers
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// Register numbers for Native code generator
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static const Register
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ZERO = { 0 },
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AT = { 1 },
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V0 = { 2 },
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V1 = { 3 },
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A0 = { 4 },
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A1 = { 5 },
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A2 = { 6 },
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A3 = { 7 },
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T0 = { 8 },
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T1 = { 9 },
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T2 = { 10 },
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T3 = { 11 },
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T4 = { 12 },
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T5 = { 13 },
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T6 = { 14 },
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T7 = { 15 },
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S0 = { 16 },
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S1 = { 17 },
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S2 = { 18 },
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S3 = { 19 },
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S4 = { 20 },
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S5 = { 21 },
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S6 = { 22 },
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S7 = { 23 },
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T8 = { 24 },
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T9 = { 25 },
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K0 = { 26 },
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K1 = { 27 },
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GP = { 28 },
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SP = { 29 },
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FP = { 30 },
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RA = { 31 },
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F0 = { 32 },
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F1 = { 33 },
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F2 = { 34 },
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F3 = { 35 },
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F4 = { 36 },
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F5 = { 37 },
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F6 = { 38 },
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F7 = { 39 },
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F8 = { 40 },
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F9 = { 41 },
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F10 = { 42 },
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F11 = { 43 },
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F12 = { 44 },
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F13 = { 45 },
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F14 = { 46 },
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F15 = { 47 },
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F16 = { 48 },
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F17 = { 49 },
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F18 = { 50 },
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F19 = { 51 },
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F20 = { 52 },
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F21 = { 53 },
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F22 = { 54 },
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F23 = { 55 },
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F24 = { 56 },
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F25 = { 57 },
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F26 = { 58 },
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F27 = { 59 },
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F28 = { 60 },
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F29 = { 61 },
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F30 = { 62 },
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F31 = { 63 },
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// FP register aliases
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FV0 = F0,
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FV1 = F2,
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FA0 = F12,
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FA1 = F14,
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FT0 = F4,
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FT1 = F6,
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FT2 = F8,
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FT3 = F10,
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FT4 = F16,
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FT5 = F18,
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FS0 = F20,
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FS1 = F22,
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FS2 = F24,
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FS3 = F26,
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FS4 = F28,
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FS5 = F30,
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deprecated_UnknownReg = { 127 }; // XXX: remove eventually, see bug 538924
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static const uint32_t FirstRegNum = ZERO;
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static const uint32_t LastRegNum = F31;
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}
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#define NJ_USE_UINT32_REGISTER 1
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#include "NativeCommon.h"
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namespace nanojit {
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// REQ: register names
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verbose_only(extern const char* regNames[];)
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// REQ: Bytes of icache to flush after Assembler::patch
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const size_t LARGEST_BRANCH_PATCH = 2 * sizeof(NIns);
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// REQ: largest value passed to underrunProtect
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static const int LARGEST_UNDERRUN_PROT = 32;
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// REQ: Number of callee saved registers
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#ifdef FPCALLEESAVED
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static const int NumSavedRegs = 14;
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#else
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static const int NumSavedRegs = 8;
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#endif
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// REQ: Callee saved registers
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const RegisterMask SavedRegs =
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#ifdef FPCALLEESAVED
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_rmask_(FS0) | _rmask_(FS1) | _rmask_(FS2) |
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_rmask_(FS3) | _rmask_(FS4) | _rmask_(FS5) |
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#endif
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_rmask_(S0) | _rmask_(S1) | _rmask_(S2) | _rmask_(S3) |
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_rmask_(S4) | _rmask_(S5) | _rmask_(S6) | _rmask_(S7);
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// REQ: General purpose registers
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static const RegisterMask GpRegs =
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_rmask_(V0) | _rmask_(V1) |
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_rmask_(A0) | _rmask_(A1) | _rmask_(A2) | _rmask_(A3) |
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_rmask_(S0) | _rmask_(S1) | _rmask_(S2) | _rmask_(S3) |
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_rmask_(S4) | _rmask_(S5) | _rmask_(S6) | _rmask_(S7) |
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_rmask_(T0) | _rmask_(T1) | _rmask_(T2) | _rmask_(T3) |
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_rmask_(T4) | _rmask_(T5) | _rmask_(T6) | _rmask_(T7) |
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_rmask_(T8) | _rmask_(T9);
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// REQ: Floating point registers
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static const RegisterMask FpRegs =
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#ifdef FPCALLEESAVED
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_rmask_(FS0) | _rmask_(FS1) | _rmask_(FS2) |
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_rmask_(FS3) | _rmask_(FS4) | _rmask_(FS5) |
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#endif
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_rmask_(FV0) | _rmask_(FV1) |
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_rmask_(FA0) | _rmask_(FA1) |
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_rmask_(FT0) | _rmask_(FT1) | _rmask_(FT2) |
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_rmask_(FT3) | _rmask_(FT4) | _rmask_(FT5);
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static const RegisterMask AllowableFlagRegs = GpRegs; // REQ: Registers that can hold flag results FIXME
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static inline bool IsFpReg(Register r)
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{
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return (_rmask_(r) & FpRegs) != 0;
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}
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static inline bool IsGpReg(Register r)
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{
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return (_rmask_(r) & GpRegs) != 0;
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}
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#define GPR(r) ((r)&31)
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#define FPR(r) ((r)&31)
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// REQ: Platform specific declarations to include in Stats structure
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#define DECLARE_PLATFORM_STATS()
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// REQ: Platform specific declarations to include in Assembler class
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#define DECLARE_PLATFORM_ASSEMBLER() \
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const static Register argRegs[4]; \
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const static Register retRegs[2]; \
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void nativePageSetup(void); \
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void nativePageReset(void); \
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void underrunProtect(int bytes); \
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bool hardenNopInsertion(const Config& /*c*/) { return false; } \
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NIns *_nSlot; \
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NIns *_nExitSlot; \
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int max_out_args; \
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Register ovreg; \
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\
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void asm_ldst(int op, Register r, int offset, Register b); \
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void asm_ldst64(bool store, Register fr, int offset, Register b); \
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void asm_store_imm64(LIns *value, int dr, Register rbase); \
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void asm_li32(Register r, int32_t imm); \
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void asm_li_d(Register fr, int32_t msw, int32_t lsw); \
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void asm_li(Register r, int32_t imm); \
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void asm_j(NIns*, bool bdelay); \
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void asm_cmp(LOpcode condop, LIns *a, LIns *b, Register cr); \
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void asm_move(Register d, Register s); \
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void asm_regarg(ArgType ty, LIns* p, Register r); \
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void asm_stkarg(LIns* arg, int stkd); \
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void asm_arg(ArgType ty, LIns* arg, Register& r, Register& fr, int& stkd); \
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void asm_arg_64(LIns* arg, Register& r, Register& fr, int& stkd); \
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NIns *asm_branchtarget(NIns*); \
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NIns *asm_bxx(bool, LOpcode, Register, Register, NIns*);
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// REQ: Platform specific declarations to include in RegAlloc class
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#define DECLARE_PLATFORM_REGALLOC()
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// REQ:
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#define swapptrs() do { \
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NIns* _tins = _nIns; _nIns = _nExitIns; _nExitIns = _tins; \
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NIns* _nslot = _nSlot; _nSlot = _nExitSlot; _nExitSlot = _nslot; \
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} while (0)
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#define TODO(x) do { verbose_only(avmplus::AvmLog(#x);) NanoAssertMsgf(false, "%s", #x); } while (0)
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#ifdef MIPSDEBUG
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#define TAG(fmt, ...) do { debug_only(verbose_outputf(" # MIPS: " fmt, ##__VA_ARGS__);) } while (0)
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#else
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#define TAG(fmt, ...) do { } while (0)
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#endif
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#define EMIT(ins, fmt, ...) do { \
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underrunProtect(4); \
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*(--_nIns) = (NIns) (ins); \
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debug_only(codegenBreak(_nIns);) \
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asm_output(fmt, ##__VA_ARGS__); \
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} while (0)
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// Emit code in trampoline/literal area
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// Assume that underrunProtect has already been called
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// This is a bit hacky...
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#define TRAMP(ins, fmt, ...) do { \
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verbose_only( \
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NIns *save_nIns = _nIns; _nIns = _nSlot; \
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) \
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*_nSlot = (NIns)ins; \
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debug_only(codegenBreak(_nSlot);) \
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_nSlot++; \
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verbose_only(setOutputForEOL("<= trampoline");) \
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asm_output(fmt, ##__VA_ARGS__); \
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verbose_only( \
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_nIns = save_nIns; \
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) \
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} while (0)
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#define MR(d, s) asm_move(d, s)
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// underrun guarantees that there is always room to insert a jump and branch delay slot
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#define JMP(t) asm_j(t, true)
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// Opcodes: bits 31..26
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#define OP_SPECIAL 0x00
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#define OP_REGIMM 0x01
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#define OP_J 0x02
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#define OP_JAL 0x03
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#define OP_BEQ 0x04
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#define OP_BNE 0x05
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#define OP_ADDIU 0x09
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#define OP_SLTIU 0x0b
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#define OP_ANDI 0x0c
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#define OP_ORI 0x0d
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#define OP_XORI 0x0e
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#define OP_LUI 0x0f
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#define OP_COP1 0x11
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#define OP_COP1X 0x13
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#define OP_SPECIAL2 0x1c
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#define OP_LB 0x20
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#define OP_LH 0x21
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#define OP_LW 0x23
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#define OP_LBU 0x24
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#define OP_LHU 0x25
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#define OP_SB 0x28
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#define OP_SH 0x29
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#define OP_SW 0x2b
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#define OP_LWC1 0x31
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#define OP_LDC1 0x35
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#define OP_SWC1 0x39
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#define OP_SDC1 0x3d
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// REGIMM: bits 20..16
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#define REGIMM_BLTZ 0x00
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#define REGIMM_BGEZ 0x01
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// COP1: bits 25..21
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#define COP1_ADD 0x00
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#define COP1_SUB 0x01
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#define COP1_MUL 0x02
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#define COP1_DIV 0x03
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#define COP1_MOV 0x06
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#define COP1_NEG 0x07
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#define COP1_BC 0x08
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#define COP1_TRUNCW 0x0d
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#define COP1_CVTD 0x21
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// COP1X: bits 5..0
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#define COP1X_LDXC1 0x01
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#define COP1X_SDXC1 0x09
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// SPECIAL: bits 5..0
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#define SPECIAL_SLL 0x00
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#define SPECIAL_MOVCI 0x01
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#define SPECIAL_SRL 0x02
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#define SPECIAL_SRA 0x03
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#define SPECIAL_SLLV 0x04
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#define SPECIAL_SRLV 0x06
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#define SPECIAL_SRAV 0x07
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#define SPECIAL_JR 0x08
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#define SPECIAL_JALR 0x09
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#define SPECIAL_MOVN 0x0b
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#define SPECIAL_MFHI 0x10
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#define SPECIAL_MFLO 0x12
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#define SPECIAL_MULT 0x18
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#define SPECIAL_ADDU 0x21
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#define SPECIAL_SUBU 0x23
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#define SPECIAL_AND 0x24
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#define SPECIAL_OR 0x25
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#define SPECIAL_XOR 0x26
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#define SPECIAL_NOR 0x27
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#define SPECIAL_SLT 0x2a
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#define SPECIAL_SLTU 0x2b
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// SPECIAL2: bits 5..0
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#define SPECIAL2_MUL 0x02
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// FORMAT: bits 25..21
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#define FMT_S 0x10
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#define FMT_D 0x11
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#define FMT_W 0x14
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#define FMT_L 0x15
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#define FMT_PS 0x16
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// CONDITION: bits 4..0
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#define COND_F 0x0
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#define COND_UN 0x1
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#define COND_EQ 0x2
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#define COND_UEQ 0x3
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#define COND_OLT 0x4
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#define COND_ULT 0x5
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#define COND_OLE 0x6
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#define COND_ULE 0x7
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#define COND_SF 0x8
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#define COND_NGLE 0x9
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#define COND_SEQ 0xa
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#define COND_NGL 0xb
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#define COND_LT 0xc
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#define COND_NGE 0xd
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#define COND_LE 0xe
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#define COND_NGT 0xf
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// Helper definitions to encode different classes of MIPS instructions
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// Parameters are in instruction order
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#define R_FORMAT(op, rs, rt, rd, re, func) \
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(((op)<<26)|(GPR(rs)<<21)|(GPR(rt)<<16)|(GPR(rd)<<11)|((re)<<6)|(func))
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#define I_FORMAT(op, rs, rt, simm) \
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(((op)<<26)|(GPR(rs)<<21)|(GPR(rt)<<16)|((simm)&0xffff))
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#define J_FORMAT(op, index) \
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(((op)<<26)|(index))
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#define U_FORMAT(op, rs, rt, uimm) \
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(((op)<<26)|(GPR(rs)<<21)|(GPR(rt)<<16)|((uimm)&0xffff))
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#define F_FORMAT(op, ffmt, ft, fs, fd, func) \
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(((op)<<26)|((ffmt)<<21)|(FPR(ft)<<16)|(FPR(fs)<<11)|(FPR(fd)<<6)|(func))
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#define oname(op) Assembler::oname[op]
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#define cname(cond) Assembler::cname[cond]
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#define fname(ffmt) Assembler::fname[ffmt]
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#define fpn(fr) gpn(fr)
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#define BOFFSET(targ) (uint32_t(targ - (_nIns+1)))
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#define LDST(op, rt, offset, base) \
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do { count_misc(); EMIT(I_FORMAT(op, base, rt, offset), \
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"%s %s, %d(%s)", oname[op], gpn(rt), offset, gpn(base)); } while (0)
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#define BX(op, rs, rt, targ) \
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do { count_br(); EMIT(I_FORMAT(op, rs, rt, BOFFSET(targ)), \
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"%s %s, %s, %p", oname[op], gpn(rt), gpn(rs), targ); } while (0)
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// MIPS instructions
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// Parameters are in "assembler" order
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#define ADDIU(rt, rs, simm) \
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do { count_alu(); EMIT(I_FORMAT(OP_ADDIU, rs, rt, simm), \
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"addiu %s, %s, %d", gpn(rt), gpn(rs), simm); } while (0)
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#define trampADDIU(rt, rs, simm) \
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do { count_alu(); TRAMP(I_FORMAT(OP_ADDIU, rs, rt, simm), \
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"addiu %s, %s, %d", gpn(rt), gpn(rs), simm); } while (0)
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#define ADDU(rd, rs, rt) \
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do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_ADDU), \
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"addu %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
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|
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#define AND(rd, rs, rt) \
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do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_AND), \
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"and %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
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#define ANDI(rt, rs, uimm) \
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do { count_alu(); EMIT(U_FORMAT(OP_ANDI, rs, rt, uimm), \
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"andi %s, %s, 0x%x", gpn(rt), gpn(rs), ((uimm)&0xffff)); } while (0)
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#define BC1F(targ) \
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do { count_br(); EMIT(I_FORMAT(OP_COP1, COP1_BC, 0, BOFFSET(targ)), \
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"bc1f %p", targ); } while (0)
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#define BC1T(targ) \
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do { count_br(); EMIT(I_FORMAT(OP_COP1, COP1_BC, 1, BOFFSET(targ)), \
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"bc1t %p", targ); } while (0)
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#define B(targ) BX(OP_BEQ, ZERO, ZERO, targ)
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#define BEQ(rs, rt, targ) BX(OP_BEQ, rs, rt, targ)
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#define BNE(rs, rt, targ) BX(OP_BNE, rs, rt, targ)
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#define BLEZ(rs, targ) BX(OP_BLEZ, rs, ZERO, targ)
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#define BGTZ(rs, targ) BX(OP_BGTZ, rs, ZERO, targ)
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#define BGEZ(rs, targ) BX(OP_REGIMM, rs, REGIMM_BGEZ, targ)
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#define BLTZ(rs, targ) BX(OP_REGIMM, rs, REGIMM_BLTZ, targ)
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#define JINDEX(dest) ((uint32_t(dest)>>2)&0x03ffffff)
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#define J(dest) \
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do { count_jmp(); EMIT(J_FORMAT(OP_J, JINDEX(dest)), \
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"j %p", dest); } while (0)
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#define trampJ(dest) \
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do { count_jmp(); TRAMP(J_FORMAT(OP_J, JINDEX(dest)), \
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"j %p", dest); } while (0)
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#define JAL(dest) \
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do { count_jmp(); EMIT(J_FORMAT(OP_JAL, JINDEX(dest)), \
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"jal %p", dest); } while (0)
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#define JALR(rs) \
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do { count_jmp(); EMIT(R_FORMAT(OP_SPECIAL, rs, 0, RA, 0, SPECIAL_JALR), \
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"jalr %s", gpn(rs)); } while (0)
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#define JR(rs) \
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do { count_jmp(); EMIT(R_FORMAT(OP_SPECIAL, rs, 0, 0, 0, SPECIAL_JR), \
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"jr %s", gpn(rs)); } while (0)
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#define trampJR(rs) \
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do { count_jmp(); TRAMP(R_FORMAT(OP_SPECIAL, rs, 0, 0, 0, SPECIAL_JR), \
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"jr %s", gpn(rs)); } while (0)
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#define LB(rt, offset, base) \
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LDST(OP_LB, rt, offset, base)
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#define LH(rt, offset, base) \
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LDST(OP_LH, rt, offset, base)
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#define LUI(rt, uimm) \
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do { count_alu(); EMIT(U_FORMAT(OP_LUI, 0, rt, uimm), \
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"lui %s, 0x%x", gpn(rt), ((uimm)&0xffff)); } while (0)
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#define LW(rt, offset, base) \
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LDST(OP_LW, rt, offset, base)
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#define MFHI(rd) \
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do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, 0, 0, rd, 0, SPECIAL_MFHI), \
|
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"mfhi %s", gpn(rd)); } while (0)
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#define MFLO(rd) \
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do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, 0, 0, rd, 0, SPECIAL_MFLO), \
|
|
"mflo %s", gpn(rd)); } while (0)
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#define MUL(rd, rs, rt) \
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do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL2, rs, rt, rd, 0, SPECIAL2_MUL), \
|
|
"mul %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
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|
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#define MULT(rs, rt) \
|
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do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, 0, 0, SPECIAL_MULT), \
|
|
"mult %s, %s", gpn(rs), gpn(rt)); } while (0)
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|
|
#define MOVE(rd, rs) \
|
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do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, ZERO, rd, 0, SPECIAL_ADDU), \
|
|
"move %s, %s", gpn(rd), gpn(rs)); } while (0)
|
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|
|
#define MOVN(rd, rs, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_MOVN), \
|
|
"movn %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
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|
|
|
#define NEGU(rd, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, ZERO, rt, rd, 0, SPECIAL_SUBU), \
|
|
"negu %s, %s", gpn(rd), gpn(rt)); } while (0)
|
|
|
|
#define NOP() \
|
|
do { count_misc(); EMIT(R_FORMAT(OP_SPECIAL, 0, 0, 0, 0, SPECIAL_SLL), \
|
|
"nop"); } while (0)
|
|
|
|
#define trampNOP() \
|
|
do { count_misc(); TRAMP(R_FORMAT(OP_SPECIAL, 0, 0, 0, 0, SPECIAL_SLL), \
|
|
"nop"); } while (0)
|
|
|
|
#define NOR(rd, rs, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_NOR), \
|
|
"nor %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
|
|
|
|
#define NOT(rd, rs) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, ZERO, rd, 0, SPECIAL_NOR), \
|
|
"not %s, %s", gpn(rd), gpn(rs)); } while (0)
|
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|
|
#define OR(rd, rs, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_OR), \
|
|
"or %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
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|
|
|
#define ORI(rt, rs, uimm) \
|
|
do { count_alu(); EMIT(U_FORMAT(OP_ORI, rs, rt, uimm), \
|
|
"ori %s, %s, 0x%x", gpn(rt), gpn(rs), ((uimm)&0xffff)); } while (0)
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|
|
|
#define SLTIU(rt, rs, simm) \
|
|
do { count_alu(); EMIT(I_FORMAT(OP_SLTIU, rs, rt, simm), \
|
|
"sltiu %s, %s, %d", gpn(rt), gpn(rs), simm); } while (0)
|
|
|
|
#define SLT(rd, rs, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_SLT), \
|
|
"slt %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
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|
|
|
#define SLTU(rd, rs, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_SLTU), \
|
|
"sltu %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
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|
|
|
#define SLL(rd, rt, sa) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, 0, rt, rd, sa, SPECIAL_SLL), \
|
|
"sll %s, %s, %d", gpn(rd), gpn(rt), sa); } while (0)
|
|
|
|
#define SLLV(rd, rt, rs) \
|
|
do { count_misc(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_SLLV), \
|
|
"sllv %s, %s, %s", gpn(rd), gpn(rt), gpn(rs)); } while (0)
|
|
|
|
#define SRA(rd, rt, sa) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, 0, rt, rd, sa, SPECIAL_SRA), \
|
|
"sra %s, %s, %d", gpn(rd), gpn(rt), sa); } while (0)
|
|
|
|
#define SRAV(rd, rt, rs) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_SRAV), \
|
|
"srav %s, %s, %s", gpn(rd), gpn(rt), gpn(rs)); } while (0)
|
|
|
|
#define SRL(rd, rt, sa) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, 0, rt, rd, sa, SPECIAL_SRL), \
|
|
"srl %s, %s, %d", gpn(rd), gpn(rt), sa); } while (0)
|
|
|
|
#define SRLV(rd, rt, rs) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_SRLV), \
|
|
"srlv %s, %s, %s", gpn(rd), gpn(rt), gpn(rs)); } while (0)
|
|
|
|
#define SUBU(rd, rs, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_SUBU), \
|
|
"subu %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
|
|
|
|
#define SW(rt, offset, base) \
|
|
LDST(OP_SW, rt, offset, base)
|
|
|
|
#define XOR(rd, rs, rt) \
|
|
do { count_alu(); EMIT(R_FORMAT(OP_SPECIAL, rs, rt, rd, 0, SPECIAL_XOR), \
|
|
"xor %s, %s, %s", gpn(rd), gpn(rs), gpn(rt)); } while (0)
|
|
|
|
#define XORI(rt, rs, uimm) \
|
|
do { count_alu(); EMIT(U_FORMAT(OP_XORI, rs, rt, uimm), \
|
|
"xori %s, %s, 0x%x", gpn(rt), gpn(rs), ((uimm)&0xffff)); } while (0)
|
|
|
|
|
|
/* FPU instructions */
|
|
#ifdef NJ_SOFTFLOAT_SUPPORTED
|
|
|
|
#if !defined(__mips_soft_float) || __mips_soft_float != 1
|
|
#error NJ_SOFTFLOAT_SUPPORTED defined but not compiled with -msoft-float
|
|
#endif
|
|
|
|
#define LWC1(ft, offset, base) NanoAssertMsg(0, "softfloat LWC1")
|
|
#define SWC1(ft, offset, base) NanoAssertMsg(0, "softfloat SWC1")
|
|
#define LDC1(ft, offset, base) NanoAssertMsg(0, "softfloat LDC1")
|
|
#define SDC1(ft, offset, base) NanoAssertMsg(0, "softfloat SDC1")
|
|
#define LDXC1(fd, index, base) NanoAssertMsg(0, "softfloat LDXC1")
|
|
#define SDXC1(fs, index, base) NanoAssertMsg(0, "softfloat SDXC1")
|
|
|
|
#define MFC1(rt, fs) NanoAssertMsg(0, "softfloat MFC1")
|
|
#define MTC1(rt, fs) NanoAssertMsg(0, "softfloat MTC1")
|
|
#define MOVF(rt, fs, cc) NanoAssertMsg(0, "softfloat MOVF")
|
|
#define CVT_D_W(fd, fs) NanoAssertMsg(0, "softfloat CVT_D_W")
|
|
#define C_EQ_D(fs, ft) NanoAssertMsg(0, "softfloat C_EQ_D")
|
|
#define C_LE_D(fs, ft) NanoAssertMsg(0, "softfloat C_LE_D")
|
|
#define C_LT_D(fs, ft) NanoAssertMsg(0, "softfloat C_LT_D")
|
|
#define ADD_D(fd, fs, ft) NanoAssertMsg(0, "softfloat ADD_D")
|
|
#define DIV_D(fd, fs, ft) NanoAssertMsg(0, "softfloat DIV_D")
|
|
#define MOV_D(fd, fs) NanoAssertMsg(0, "softfloat MOV_D")
|
|
#define MUL_D(fd, fs, ft) NanoAssertMsg(0, "softfloat MUL_D")
|
|
#define NEG_D(fd, fs) NanoAssertMsg(0, "softfloat NEG_D")
|
|
#define SUB_D(fd, fs, ft) NanoAssertMsg(0, "softfloat SUB_D")
|
|
#define TRUNC_W_D(fd,fs) NanoAssertMsg(0, "softfloat TRUNC_W_D")
|
|
|
|
#else
|
|
|
|
#if defined(__mips_soft_float) && __mips_soft_float != 0
|
|
#error compiled with -msoft-float but NJ_SOFTFLOAT_SUPPORTED not defined
|
|
#endif
|
|
|
|
#define FOP_FMT2(ffmt, fd, fs, func, name) \
|
|
do { count_fpu(); EMIT(F_FORMAT(OP_COP1, ffmt, 0, fs, fd, func), \
|
|
"%s.%s %s, %s", name, fname[ffmt], fpn(fd), fpn(fs)); } while (0)
|
|
|
|
#define FOP_FMT3(ffmt, fd, fs, ft, func, name) \
|
|
do { count_fpu(); EMIT(F_FORMAT(OP_COP1, ffmt, ft, fs, fd, func), \
|
|
"%s.%s %s, %s, %s", name, fname[ffmt], fpn(fd), fpn(fs), fpn(ft)); } while (0)
|
|
|
|
#define C_COND_FMT(cond, ffmt, fs, ft) \
|
|
do { count_fpu(); EMIT(F_FORMAT(OP_COP1, ffmt, ft, fs, 0, 0x30|(cond)), \
|
|
"c.%s.%s %s, %s", cname[cond], fname[ffmt], fpn(fs), fpn(ft)); } while (0)
|
|
|
|
#define MFC1(rt, fs) \
|
|
do { count_fpu(); EMIT(F_FORMAT(OP_COP1, 0, rt, fs, 0, 0), \
|
|
"mfc1 %s, %s", gpn(rt), fpn(fs)); } while (0)
|
|
|
|
#define MTC1(rt, fs) \
|
|
do { count_fpu(); EMIT(F_FORMAT(OP_COP1, 4, rt, fs, 0, 0), \
|
|
"mtc1 %s, %s", gpn(rt), fpn(fs)); } while (0)
|
|
|
|
#define MOVF(rd, rs, cc) \
|
|
do { count_fpu(); EMIT(R_FORMAT(OP_SPECIAL, rs, (cc)<<2, rd, 0, SPECIAL_MOVCI), \
|
|
"movf %s, %s, $fcc%d", gpn(rd), gpn(rs), cc); } while (0)
|
|
|
|
#define CVT_D_W(fd, fs) \
|
|
do { count_fpu(); EMIT(F_FORMAT(OP_COP1, FMT_W, 0, fs, fd, COP1_CVTD), \
|
|
"cvt.d.w %s, %s", fpn(fd), fpn(fs)); } while (0)
|
|
|
|
#define TRUNC_W_D(fd, fs) \
|
|
do { count_fpu(); EMIT(F_FORMAT(OP_COP1, FMT_D, 0, fs, fd, COP1_TRUNCW), \
|
|
"trunc.w.d %s, %s", fpn(fd), fpn(fs)); } while (0)
|
|
|
|
|
|
#define LWC1(ft, offset, base) LDST(OP_LWC1, ft, offset, base)
|
|
#define SWC1(ft, offset, base) LDST(OP_SWC1, ft, offset, base)
|
|
#define LDC1(ft, offset, base) LDST(OP_LDC1, ft, offset, base)
|
|
#define SDC1(ft, offset, base) LDST(OP_SDC1, ft, offset, base)
|
|
#define LDXC1(fd, index, base) \
|
|
do { count_fpu(); EMIT(R_FORMAT(OP_COP1X, base, index, 0, fd, COP1X_LDXC1), \
|
|
"ldxc1 %s, %s(%s)", fpn(fd), gpn(index), gpn(base)); } while (0)
|
|
#define SDXC1(fs, index, base) \
|
|
do { count_fpu(); EMIT(R_FORMAT(OP_COP1X, base, index, fs, 0, COP1X_SDXC1), \
|
|
"sdxc1 %s, %s(%s)", fpn(fs), gpn(index), gpn(base)); } while (0)
|
|
|
|
#define C_EQ_D(fs, ft) C_COND_FMT(COND_EQ, FMT_D, fs, ft)
|
|
#define C_LE_D(fs, ft) C_COND_FMT(COND_LE, FMT_D, fs, ft)
|
|
#define C_LT_D(fs, ft) C_COND_FMT(COND_LT, FMT_D, fs, ft)
|
|
#define ADD_D(fd, fs, ft) FOP_FMT3(FMT_D, fd, fs, ft, COP1_ADD, "add")
|
|
#define DIV_D(fd, fs, ft) FOP_FMT3(FMT_D, fd, fs, ft, COP1_DIV, "div")
|
|
#define MOV_D(fd, fs) FOP_FMT2(FMT_D, fd, fs, COP1_MOV, "mov")
|
|
#define MUL_D(fd, fs, ft) FOP_FMT3(FMT_D, fd, fs, ft, COP1_MUL, "mul")
|
|
#define NEG_D(fd, fs) FOP_FMT2(FMT_D, fd, fs, COP1_NEG, "neg")
|
|
#define SUB_D(fd, fs, ft) FOP_FMT3(FMT_D, fd, fs, ft, COP1_SUB, "sub")
|
|
#endif
|
|
|
|
}
|
|
#endif // __nanojit_NativeMIPS__
|