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[JAEGER] Implement branchTruncateDoubleToInt32 for ARM. [Bug 585918] [r=dmandelin]
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@ -205,6 +205,7 @@ namespace JSC {
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FMRS = 0x0e100a10,
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FSITOD = 0x0eb80bc0,
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FTOSID = 0x0ebd0b40,
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FTOSIZD = 0x0ebd0bc0,
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FMSTAT = 0x0ef1fa10
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#if WTF_ARM_ARCH_VERSION >= 5
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,CLZ = 0x016f0f10,
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@ -426,6 +427,12 @@ namespace JSC {
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emitInst(static_cast<ARMWord>(cc) | CMP | SET_CC, 0, rn, op2);
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}
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void cmn_r(int rn, ARMWord op2, Condition cc = AL)
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{
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spewInsWithOp2("cmn", cc, rn, op2);
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emitInst(static_cast<ARMWord>(cc) | CMN | SET_CC, 0, rn, op2);
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}
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void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
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{
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spewInsWithOp2("orr", cc, rd, rn, op2);
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@ -673,16 +680,18 @@ namespace JSC {
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void fdtr_u(bool isLoad, int dd, int rn, ARMWord offset, Condition cc = AL)
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{
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char const * ins = isLoad ? "vldr.f64" : "vstr.f64";
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js::JaegerSpew(js::JSpew_Insns,
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IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, "vldr.f64", nameFpRegD(dd), nameGpReg(rn), offset);
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IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, ins, nameFpRegD(dd), nameGpReg(rn), offset);
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ASSERT(offset <= 0xff);
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emitInst(static_cast<ARMWord>(cc) | FDTR | DT_UP | (isLoad ? DT_LOAD : 0), dd, rn, offset);
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}
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void fdtr_d(bool isLoad, int dd, int rn, ARMWord offset, Condition cc = AL)
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{
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char const * ins = isLoad ? "vldr.f64" : "vstr.f64";
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js::JaegerSpew(js::JSpew_Insns,
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IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, "vldr.f64", nameFpRegD(dd), nameGpReg(rn), offset);
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IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, ins, nameFpRegD(dd), nameGpReg(rn), offset);
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ASSERT(offset <= 0xff);
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emitInst(static_cast<ARMWord>(cc) | FDTR | (isLoad ? DT_LOAD : 0), dd, rn, offset);
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}
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@ -741,6 +750,13 @@ namespace JSC {
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emitInst(static_cast<ARMWord>(cc) | FTOSID, fd, 0, dm);
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}
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void ftosizd_r(int fd, int dm, Condition cc = AL)
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{
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// TODO: emitInst doesn't work for VFP instructions, though it
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// seems to work for current usage.
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emitInst(static_cast<ARMWord>(cc) | FTOSIZD, fd, 0, dm);
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}
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void fmstat(Condition cc = AL)
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{
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// TODO: emitInst doesn't work for VFP instructions, though it
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@ -853,7 +853,7 @@ public:
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bool supportsFloatingPointTruncate() const
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{
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return false;
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return true;
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}
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bool supportsFloatingPointSqrt() const
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@ -972,13 +972,17 @@ public:
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// Truncates 'src' to an integer, and places the resulting 'dest'.
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// If the result is not representable as a 32 bit value, branch.
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// May also branch for some values that are representable in 32 bits
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// (specifically, in this case, INT_MIN).
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// (specifically, in this case, INT_MIN and INT_MAX).
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Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
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{
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(void)(src);
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(void)(dest);
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ASSERT_NOT_REACHED();
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return jump();
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m_assembler.ftosizd_r(ARMRegisters::SD0, src);
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// If FTOSIZD (VCVT.S32.F64) can't fit the result into a 32-bit
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// integer, it saturates at INT_MAX or INT_MIN. Testing this is
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// probably quicker than testing FPSCR for exception.
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m_assembler.fmrs_r(dest, ARMRegisters::SD0);
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m_assembler.cmn_r(dest, ARMAssembler::getOp2(1));
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m_assembler.cmp_r(dest, ARMAssembler::getOp2(0x80000000), ARMCondition(NonZero));
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return Jump(m_assembler.jmp(ARMCondition(Zero)));
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}
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// Convert 'src' to an integer, and places the resulting 'dest'.
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