mirror of
https://gitlab.winehq.org/wine/wine-gecko.git
synced 2024-09-13 09:24:08 -07:00
Bug 915833 - SpiderMonkey: Add support for immediate addresses on x64. r=sstangl
This commit is contained in:
Dan Gohman
parent
2f0a25f9b6
commit
f679cd4daa
@ -561,6 +561,13 @@ public:
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m_formatter.oneByteOp64(OP_ADD_GvEv, dst, base, offset);
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}
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void addq_mr(const void* addr, RegisterID dst)
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{
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spew("addq %p, %s",
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addr, nameIReg(8, dst));
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m_formatter.oneByteOp64(OP_ADD_GvEv, dst, addr);
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}
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void addq_ir(int imm, RegisterID dst)
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{
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spew("addq $0x%x, %s", imm, nameIReg(8,dst));
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@ -585,10 +592,22 @@ public:
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m_formatter.immediate32(imm);
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}
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}
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#else
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void addq_im(int imm, const void* addr)
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{
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spew("addq %d, %p", imm, addr);
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if (CAN_SIGN_EXTEND_8_32(imm)) {
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m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, addr);
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m_formatter.immediate8(imm);
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} else {
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m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, addr);
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m_formatter.immediate32(imm);
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}
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}
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#endif
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void addl_im(int imm, const void* addr)
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{
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FIXME_INSN_PRINTING;
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spew("addl %d, %p", imm, addr);
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if (CAN_SIGN_EXTEND_8_32(imm)) {
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m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, addr);
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m_formatter.immediate8(imm);
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@ -597,7 +616,6 @@ public:
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m_formatter.immediate32(imm);
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}
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}
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#endif
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void andl_rr(RegisterID src, RegisterID dst)
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{
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@ -665,6 +683,13 @@ public:
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m_formatter.oneByteOp64(OP_OR_GvEv, dst, base, offset);
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}
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void orq_mr(const void* addr, RegisterID dst)
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{
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spew("orq %p, %s",
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addr, nameIReg(8, dst));
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m_formatter.oneByteOp64(OP_OR_GvEv, dst, addr);
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}
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void andq_ir(int imm, RegisterID dst)
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{
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spew("andq $0x%x, %s", imm, nameIReg(8,dst));
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@ -878,6 +903,13 @@ public:
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m_formatter.oneByteOp64(OP_SUB_GvEv, dst, base, offset);
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}
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void subq_mr(const void* addr, RegisterID dst)
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{
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spew("subq %p, %s",
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addr, nameIReg(8, dst));
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m_formatter.oneByteOp64(OP_SUB_GvEv, dst, addr);
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}
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void subq_ir(int imm, RegisterID dst)
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{
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spew("subq $0x%x, %s", imm, nameIReg(8,dst));
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@ -1254,7 +1286,23 @@ public:
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m_formatter.immediate32(imm);
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}
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}
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#else
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void cmpq_im(int imm, const void* addr)
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{
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spew("cmpq $0x%x, %p", imm, addr);
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if (CAN_SIGN_EXTEND_8_32(imm)) {
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m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_CMP, addr);
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m_formatter.immediate8(imm);
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} else {
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m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_CMP, addr);
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m_formatter.immediate32(imm);
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}
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}
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void cmpq_rm(RegisterID reg, const void* addr)
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{
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spew("cmpq %s, %p", nameIReg(8, reg), addr);
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m_formatter.oneByteOp64(OP_CMP_EvGv, reg, addr);
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}
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#endif
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void cmpl_rm(RegisterID reg, const void* addr)
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{
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spew("cmpl %s, %p",
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@ -1273,7 +1321,6 @@ public:
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m_formatter.immediate32(imm);
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}
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}
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#endif
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void cmpw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
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{
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@ -1558,14 +1605,14 @@ public:
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m_formatter.oneByteOp_disp32(OP_MOV_GvEv, dst, base, offset);
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}
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#if WTF_CPU_X86
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void movl_mr(const void* base, RegisterID index, int scale, RegisterID dst)
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{
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int32_t disp = addressImmediate(base);
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spew("movl %d(,%s,%d), %s",
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int(base), nameIReg(index), scale, nameIReg(dst));
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m_formatter.oneByteOp_disp32(OP_MOV_GvEv, dst, index, scale, int(base));
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disp, nameIReg(index), scale, nameIReg(dst));
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m_formatter.oneByteOp_disp32(OP_MOV_GvEv, dst, index, scale, disp);
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}
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#endif
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void movl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
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{
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@ -1574,7 +1621,6 @@ public:
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m_formatter.oneByteOp(OP_MOV_GvEv, dst, base, index, scale, offset);
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}
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#if !WTF_CPU_X86_64
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void movl_mr(const void* addr, RegisterID dst)
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{
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spew("movl %p, %s",
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@ -1584,7 +1630,6 @@ public:
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else
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m_formatter.oneByteOp(OP_MOV_GvEv, dst, addr);
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}
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#endif
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void movl_i32r(int imm, RegisterID dst)
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{
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@ -1683,6 +1728,16 @@ public:
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m_formatter.oneByteOp64(OP_MOV_EvGv, src, base, index, scale, offset);
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}
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void movq_rm(RegisterID src, const void* addr)
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{
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spew("movq %s, %p",
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nameIReg(8, src), addr);
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if (src == X86Registers::eax)
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movq_EAXm(addr);
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else
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m_formatter.oneByteOp64(OP_MOV_EvGv, src, addr);
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}
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void movq_mEAX(const void* addr)
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{
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FIXME_INSN_PRINTING;
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@ -1717,6 +1772,16 @@ public:
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m_formatter.oneByteOp64(OP_MOV_GvEv, dst, base, index, scale, offset);
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}
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void movq_mr(const void* addr, RegisterID dst)
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{
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spew("movq %p, %s",
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addr, nameIReg(8, dst));
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if (dst == X86Registers::eax)
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movq_mEAX(addr);
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else
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m_formatter.oneByteOp64(OP_MOV_GvEv, dst, addr);
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}
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void leaq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
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{
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spew("leaq %d(%s,%s,%d), %s",
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@ -1739,6 +1804,12 @@ public:
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m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, base, index, scale, offset);
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m_formatter.immediate32(imm);
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}
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void movq_i32m(int imm, const void* addr)
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{
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spew("movq %d, %p", imm, addr);
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m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, addr);
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m_formatter.immediate32(imm);
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}
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// Note that this instruction sign-extends its 32-bit immediate field to 64
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// bits and loads the 64-bit value into a 64-bit register.
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@ -1791,7 +1862,7 @@ public:
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m_formatter.oneByteRipOp64(OP_MOV_GvEv, dst, 0);
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return JmpSrc(m_formatter.size());
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}
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#else
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#endif
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void movl_rm(RegisterID src, const void* addr)
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{
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spew("movl %s, %p",
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@ -1804,11 +1875,10 @@ public:
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void movl_i32m(int imm, const void* addr)
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{
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FIXME_INSN_PRINTING;
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spew("movl %d, %p", imm, addr);
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m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, addr);
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m_formatter.immediate32(imm);
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}
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#endif
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void movb_rm(RegisterID src, int offset, RegisterID base)
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{
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@ -2205,7 +2275,6 @@ public:
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m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, base, offset);
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}
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#if !WTF_CPU_X86_64
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void addsd_mr(const void* address, XMMRegisterID dst)
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{
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spew("addsd %p, %s",
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@ -2220,7 +2289,6 @@ public:
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m_formatter.prefix(PRE_SSE_F3);
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m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, address);
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}
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#endif
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void cvtss2sd_rr(XMMRegisterID src, XMMRegisterID dst)
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{
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@ -3144,6 +3212,26 @@ public:
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reinterpret_cast<const void**>(where)[-1] = value;
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}
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// Test whether the given address will fit in an address immediate field.
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// This is always true on x86, but on x64 it's only true for addreses
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// which fit in the 32-bit immediate field.
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static bool isAddressImmediate(const void *address) {
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intptr_t value = reinterpret_cast<intptr_t>(address);
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int32_t immediate = static_cast<int32_t>(value);
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return value == immediate;
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}
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// Convert the given address to a 32-bit immediate field value. This is
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// a no-op on x86, but on x64 it asserts that the address is actually
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// a valid address immediate.
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static int32_t addressImmediate(const void *address) {
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#if WTF_CPU_X86_64
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// x64's 64-bit addresses don't all fit in the 32-bit immediate.
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ASSERT(isAddressImmediate(address));
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#endif
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return static_cast<int32_t>(reinterpret_cast<intptr_t>(address));
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}
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private:
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static int32_t getInt32(void* where)
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@ -3237,14 +3325,13 @@ private:
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memoryModRM_disp32(reg, index, scale, offset);
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}
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#if !WTF_CPU_X86_64
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void oneByteOp(OneByteOpcodeID opcode, int reg, const void* address)
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{
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m_buffer.ensureSpace(maxInstructionSize);
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m_buffer.putByteUnchecked(opcode);
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memoryModRM(reg, address);
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}
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#else
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#if WTF_CPU_X86_64
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void oneByteRipOp(OneByteOpcodeID opcode, int reg, int ripOffset)
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{
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m_buffer.ensureSpace(maxInstructionSize);
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@ -3317,7 +3404,6 @@ private:
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memoryModRM(reg, base, index, scale, offset);
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}
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#if !WTF_CPU_X86_64
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void twoByteOp(TwoByteOpcodeID opcode, int reg, const void* address)
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{
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m_buffer.ensureSpace(maxInstructionSize);
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@ -3325,7 +3411,6 @@ private:
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m_buffer.putByteUnchecked(opcode);
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memoryModRM(reg, address);
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}
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#endif
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void threeByteOp(ThreeByteOpcodeID opcode, ThreeByteEscape escape, int reg, RegisterID rm)
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{
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@ -3400,6 +3485,14 @@ private:
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memoryModRM(reg, base, index, scale, offset);
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}
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void oneByteOp64(OneByteOpcodeID opcode, int reg, const void* address)
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{
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m_buffer.ensureSpace(maxInstructionSize);
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emitRexW(reg, 0, 0);
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m_buffer.putByteUnchecked(opcode);
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memoryModRM(reg, address);
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}
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void twoByteOp64(TwoByteOpcodeID opcode, int reg, RegisterID rm)
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{
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m_buffer.ensureSpace(maxInstructionSize);
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@ -3766,14 +3859,19 @@ private:
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m_buffer.putIntUnchecked(offset);
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}
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#if !WTF_CPU_X86_64
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void memoryModRM(int reg, const void* address)
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{
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int32_t disp = addressImmediate(address);
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#if WTF_CPU_X86_64
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// On x64-64, non-RIP-relative absolute mode requires a SIB.
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putModRmSib(ModRmMemoryNoDisp, reg, noBase, noIndex, 0);
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#else
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// noBase + ModRmMemoryNoDisp means noBase + ModRmMemoryDisp32!
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putModRm(ModRmMemoryNoDisp, reg, noBase);
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m_buffer.putIntUnchecked(reinterpret_cast<int32_t>(address));
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}
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#endif
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m_buffer.putIntUnchecked(disp);
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}
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AssemblerBuffer m_buffer;
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} m_formatter;
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@ -248,11 +248,9 @@ class AssemblerX86Shared
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case Operand::MEM_SCALE:
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masm.movl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.movl_mr(src.address(), dest.code());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -268,11 +266,9 @@ class AssemblerX86Shared
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case Operand::MEM_SCALE:
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masm.movl_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.movl_rm(src.code(), dest.address());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -737,11 +733,9 @@ class AssemblerX86Shared
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case Operand::MEM_SCALE:
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masm.cmpl_im(imm.value, op.disp(), op.base(), op.index(), op.scale());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.cmpl_im(imm.value, op.address());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -754,11 +748,9 @@ class AssemblerX86Shared
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case Operand::MEM_REG_DISP:
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masm.cmpl_rm(rhs.code(), lhs.disp(), lhs.base());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.cmpl_rm(rhs.code(), lhs.address());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -771,11 +763,9 @@ class AssemblerX86Shared
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case Operand::MEM_REG_DISP:
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masm.cmpl_im(imm.value, op.disp(), op.base());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.cmpl_im(imm.value, op.address());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -822,11 +812,9 @@ class AssemblerX86Shared
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case Operand::MEM_REG_DISP:
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masm.addl_im(imm.value, op.disp(), op.base());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.addl_im(imm.value, op.address());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -1227,11 +1215,9 @@ class AssemblerX86Shared
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case Operand::MEM_REG_DISP:
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masm.addsd_mr(src.disp(), src.base(), dest.code());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.addsd_mr(src.address(), dest.code());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -1245,11 +1231,9 @@ class AssemblerX86Shared
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case Operand::MEM_REG_DISP:
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masm.addss_mr(src.disp(), src.base(), dest.code());
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break;
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#ifdef JS_CPU_X86
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case Operand::MEM_ADDRESS:
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case Operand::MEM_ADDRESS32:
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masm.addss_mr(src.address(), dest.code());
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break;
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#endif
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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@ -175,11 +175,12 @@ class Operand
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REG,
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MEM_REG_DISP,
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FPREG,
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MEM_SCALE
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MEM_SCALE,
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MEM_ADDRESS32
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};
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private:
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Kind kind_ : 3;
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Kind kind_ : 4;
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int32_t base_ : 5;
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Scale scale_ : 3;
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int32_t index_ : 5;
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@ -218,6 +219,11 @@ class Operand
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base_(reg.code()),
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disp_(disp)
|
||||
{ }
|
||||
explicit Operand(const AbsoluteAddress &address)
|
||||
: kind_(MEM_ADDRESS32)
|
||||
{
|
||||
disp_ = JSC::X86Assembler::addressImmediate(address.addr);
|
||||
}
|
||||
|
||||
Address toAddress() const {
|
||||
JS_ASSERT(kind() == MEM_REG_DISP);
|
||||
@ -256,6 +262,10 @@ class Operand
|
||||
JS_ASSERT(kind() == MEM_REG_DISP || kind() == MEM_SCALE);
|
||||
return disp_;
|
||||
}
|
||||
void *address() const {
|
||||
JS_ASSERT(kind() == MEM_ADDRESS32);
|
||||
return reinterpret_cast<void *>(intptr_t(disp_));
|
||||
}
|
||||
};
|
||||
|
||||
} // namespace jit
|
||||
@ -410,6 +420,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_SCALE:
|
||||
masm.movq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.movq_mr(src.address(), dest.code());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -425,6 +438,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_SCALE:
|
||||
masm.movq_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.movq_rm(src.code(), dest.address());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -440,6 +456,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_SCALE:
|
||||
masm.movq_i32m(imm32.value, dest.disp(), dest.base(), dest.index(), dest.scale());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.movq_i32m(imm32.value, dest.address());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -476,6 +495,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_REG_DISP:
|
||||
masm.addq_im(imm.value, dest.disp(), dest.base());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.addq_im(imm.value, dest.address());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -491,6 +513,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_REG_DISP:
|
||||
masm.addq_mr(src.disp(), src.base(), dest.code());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.addq_mr(src.address(), dest.code());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -510,6 +535,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_REG_DISP:
|
||||
masm.subq_mr(src.disp(), src.base(), dest.code());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.subq_mr(src.address(), dest.code());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -537,6 +565,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_REG_DISP:
|
||||
masm.orq_mr(src.disp(), src.base(), dest.code());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.orq_mr(src.address(), dest.code());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -622,6 +653,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_REG_DISP:
|
||||
masm.cmpq_rm(rhs.code(), lhs.disp(), lhs.base());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.cmpq_rm(rhs.code(), lhs.address());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
@ -634,6 +668,9 @@ class Assembler : public AssemblerX86Shared
|
||||
case Operand::MEM_REG_DISP:
|
||||
masm.cmpq_im(rhs.value, lhs.disp(), lhs.base());
|
||||
break;
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.cmpq_im(rhs.value, lhs.address());
|
||||
break;
|
||||
default:
|
||||
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
|
||||
}
|
||||
|
||||
@ -509,20 +509,32 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
|
||||
}
|
||||
|
||||
void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
|
||||
if (JSC::X86Assembler::isAddressImmediate(lhs.addr)) {
|
||||
branch32(cond, Operand(lhs), rhs, label);
|
||||
} else {
|
||||
mov(ImmPtr(lhs.addr), ScratchReg);
|
||||
branch32(cond, Address(ScratchReg, 0), rhs, label);
|
||||
}
|
||||
}
|
||||
void branch32(Condition cond, const AbsoluteAddress &lhs, Register rhs, Label *label) {
|
||||
if (JSC::X86Assembler::isAddressImmediate(lhs.addr)) {
|
||||
branch32(cond, Operand(lhs), rhs, label);
|
||||
} else {
|
||||
mov(ImmPtr(lhs.addr), ScratchReg);
|
||||
branch32(cond, Address(ScratchReg, 0), rhs, label);
|
||||
}
|
||||
}
|
||||
|
||||
// Specialization for AbsoluteAddress.
|
||||
void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) {
|
||||
JS_ASSERT(ptr != ScratchReg);
|
||||
if (JSC::X86Assembler::isAddressImmediate(addr.addr)) {
|
||||
branchPtr(cond, Operand(addr), ptr, label);
|
||||
} else {
|
||||
mov(ImmPtr(addr.addr), ScratchReg);
|
||||
branchPtr(cond, Operand(ScratchReg, 0x0), ptr, label);
|
||||
}
|
||||
}
|
||||
|
||||
void branchPrivatePtr(Condition cond, Address lhs, ImmPtr ptr, Label *label) {
|
||||
branchPtr(cond, lhs, ImmWord(uintptr_t(ptr.value) >> 1), label);
|
||||
@ -593,9 +605,13 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
|
||||
movq(imm, dest);
|
||||
}
|
||||
void loadPtr(const AbsoluteAddress &address, Register dest) {
|
||||
if (JSC::X86Assembler::isAddressImmediate(address.addr)) {
|
||||
movq(Operand(address), dest);
|
||||
} else {
|
||||
mov(ImmPtr(address.addr), ScratchReg);
|
||||
movq(Operand(ScratchReg, 0x0), dest);
|
||||
}
|
||||
}
|
||||
void loadPtr(const Address &address, Register dest) {
|
||||
movq(Operand(address), dest);
|
||||
}
|
||||
@ -631,9 +647,13 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
|
||||
movq(src, dest);
|
||||
}
|
||||
void storePtr(const Register &src, const AbsoluteAddress &address) {
|
||||
if (JSC::X86Assembler::isAddressImmediate(address.addr)) {
|
||||
movq(src, Operand(address));
|
||||
} else {
|
||||
mov(ImmPtr(address.addr), ScratchReg);
|
||||
movq(src, Operand(ScratchReg, 0x0));
|
||||
}
|
||||
}
|
||||
void rshiftPtr(Imm32 imm, Register dest) {
|
||||
shrq(imm, dest);
|
||||
}
|
||||
@ -1065,9 +1085,13 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
|
||||
}
|
||||
|
||||
void inc64(AbsoluteAddress dest) {
|
||||
if (JSC::X86Assembler::isAddressImmediate(dest.addr)) {
|
||||
addPtr(Imm32(1), Operand(dest));
|
||||
} else {
|
||||
mov(ImmPtr(dest.addr), ScratchReg);
|
||||
addPtr(Imm32(1), Address(ScratchReg, 0));
|
||||
}
|
||||
}
|
||||
|
||||
// If source is a double, load it into dest. If source is int32,
|
||||
// convert it to double. Else, branch to failure.
|
||||
|
||||
@ -116,7 +116,7 @@ class Operand
|
||||
MEM_REG_DISP,
|
||||
FPREG,
|
||||
MEM_SCALE,
|
||||
MEM_ADDRESS
|
||||
MEM_ADDRESS32
|
||||
};
|
||||
|
||||
private:
|
||||
@ -160,11 +160,11 @@ class Operand
|
||||
disp_(disp)
|
||||
{ }
|
||||
explicit Operand(const AbsoluteAddress &address)
|
||||
: kind_(MEM_ADDRESS),
|
||||
: kind_(MEM_ADDRESS32),
|
||||
disp_(reinterpret_cast<int32_t>(address.addr))
|
||||
{ }
|
||||
explicit Operand(const void *address)
|
||||
: kind_(MEM_ADDRESS),
|
||||
: kind_(MEM_ADDRESS32),
|
||||
disp_(reinterpret_cast<int32_t>(address))
|
||||
{ }
|
||||
|
||||
@ -206,7 +206,7 @@ class Operand
|
||||
return disp_;
|
||||
}
|
||||
void *address() const {
|
||||
JS_ASSERT(kind() == MEM_ADDRESS);
|
||||
JS_ASSERT(kind() == MEM_ADDRESS32);
|
||||
return reinterpret_cast<void *>(disp_);
|
||||
}
|
||||
};
|
||||
@ -386,7 +386,7 @@ class Assembler : public AssemblerX86Shared
|
||||
masm.cmpl_im_force32(imm.value, op.disp(), op.base());
|
||||
writeDataRelocation(imm);
|
||||
break;
|
||||
case Operand::MEM_ADDRESS:
|
||||
case Operand::MEM_ADDRESS32:
|
||||
masm.cmpl_im(imm.value, op.address());
|
||||
writeDataRelocation(imm);
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user