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https://gitlab.winehq.org/wine/wine-gecko.git
synced 2024-09-13 09:24:08 -07:00
change 71a045ccce43 inadvertently backed out change b8f64e82da3f; this restores the latter (r=stejohns)
--HG-- extra : convert_revision : 2fbb1bbebee5e0872ea3d485a40d7f71f785f319
This commit is contained in:
Steven Johnson
parent
ea07a846cc
commit
eecc554117
@ -214,8 +214,8 @@ namespace nanojit
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switch (ins->opcode()) {
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case LIR_ldf:
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case LIR_ldfc:
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case LIR_ldq:
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case LIR_ldqc:
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CASE64(LIR_ldq:)
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CASE64(LIR_ldqc:)
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// handled by mainline code below for now
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break;
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case LIR_ld32f:
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@ -308,7 +308,7 @@ namespace nanojit
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switch (op) {
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case LIR_stfi:
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case LIR_stqi:
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CASE64(LIR_stqi:)
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// handled by mainline code below for now
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break;
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case LIR_st32f:
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@ -321,18 +321,6 @@ namespace nanojit
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Register ra = getBaseReg(base, dr, GpRegs);
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#if !PEDANTIC && !defined NANOJIT_64BIT
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if (value->isop(LIR_quad) && isS16(dr) && isS16(dr+4)) {
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// quad constant and short offset
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uint64_t q = value->imm64();
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STW(R0, dr, ra); // hi
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asm_li(R0, int32_t(q>>32)); // hi
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STW(R0, dr+4, ra); // lo
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asm_li(R0, int32_t(q)); // lo
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return;
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}
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#endif // !PEDANTIC
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// general case for any value
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#if !defined NANOJIT_64BIT
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// on 32bit cpu's, we only use store64 for doubles
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@ -379,30 +367,30 @@ namespace nanojit
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Register r = deprecated_prepResultReg(ins, GpRegs);
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switch (op) {
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case LIR_eq: case LIR_feq:
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case LIR_qeq:
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CASE64(LIR_qeq:)
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EXTRWI(r, r, 1, 4*cr+COND_eq); // extract CR7.eq
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MFCR(r);
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break;
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case LIR_lt: case LIR_ult:
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case LIR_flt: case LIR_fle:
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case LIR_qlt: case LIR_qult:
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CASE64(LIR_qlt:) CASE64(LIR_qult:)
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EXTRWI(r, r, 1, 4*cr+COND_lt); // extract CR7.lt
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MFCR(r);
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break;
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case LIR_gt: case LIR_ugt:
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case LIR_fgt: case LIR_fge:
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case LIR_qgt: case LIR_qugt:
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CASE64(LIR_qgt:) CASE64(LIR_qugt:)
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EXTRWI(r, r, 1, 4*cr+COND_gt); // extract CR7.gt
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MFCR(r);
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break;
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case LIR_le: case LIR_ule:
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case LIR_qle: case LIR_qule:
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CASE64(LIR_qle:) CASE64(LIR_qule:)
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EXTRWI(r, r, 1, 4*cr+COND_eq); // extract CR7.eq
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MFCR(r);
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CROR(CR7, eq, lt, eq);
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break;
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case LIR_ge: case LIR_uge:
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case LIR_qge: case LIR_quge:
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CASE64(LIR_qge:) CASE64(LIR_quge:)
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EXTRWI(r, r, 1, 4*cr+COND_eq); // select CR7.eq
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MFCR(r);
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CROR(CR7, eq, gt, eq);
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@ -469,25 +457,25 @@ namespace nanojit
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switch (cond->opcode()) {
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case LIR_eq:
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case LIR_feq:
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case LIR_qeq:
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CASE64(LIR_qeq:)
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if (onfalse) BNE(cr,bd); else BEQ(cr,bd);
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break;
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case LIR_lt: case LIR_ult:
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case LIR_flt: case LIR_fle:
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case LIR_qlt: case LIR_qult:
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CASE64(LIR_qlt:) CASE64(LIR_qult:)
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if (onfalse) BNL(cr,bd); else BLT(cr,bd);
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break;
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case LIR_le: case LIR_ule:
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case LIR_qle: case LIR_qule:
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CASE64(LIR_qle:) CASE64(LIR_qule:)
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if (onfalse) BGT(cr,bd); else BLE(cr,bd);
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break;
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case LIR_gt: case LIR_ugt:
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case LIR_fgt: case LIR_fge:
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case LIR_qgt: case LIR_qugt:
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CASE64(LIR_qgt:) CASE64(LIR_qugt:)
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if (onfalse) BNG(cr,bd); else BGT(cr,bd);
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break;
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case LIR_ge: case LIR_uge:
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case LIR_qge: case LIR_quge:
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CASE64(LIR_qge:) CASE64(LIR_quge:)
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if (onfalse) BLT(cr,bd); else BGE(cr,bd);
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break;
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default:
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@ -507,25 +495,25 @@ namespace nanojit
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switch (condop) {
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case LIR_eq:
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case LIR_feq:
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case LIR_qeq:
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CASE64(LIR_qeq:)
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if (onfalse) BNECTR(cr); else BEQCTR(cr);
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break;
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case LIR_lt: case LIR_ult:
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case LIR_qlt: case LIR_qult:
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CASE64(LIR_qlt:) CASE64(LIR_qult:)
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case LIR_flt: case LIR_fle:
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if (onfalse) BNLCTR(cr); else BLTCTR(cr);
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break;
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case LIR_le: case LIR_ule:
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case LIR_qle: case LIR_qule:
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CASE64(LIR_qle:) CASE64(LIR_qule:)
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if (onfalse) BGTCTR(cr); else BLECTR(cr);
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break;
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case LIR_gt: case LIR_ugt:
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case LIR_qgt: case LIR_qugt:
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CASE64(LIR_qgt:) CASE64(LIR_qugt:)
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case LIR_fgt: case LIR_fge:
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if (onfalse) BNGCTR(cr); else BGTCTR(cr);
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break;
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case LIR_ge: case LIR_uge:
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case LIR_qge: case LIR_quge:
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CASE64(LIR_qge:) CASE64(LIR_quge:)
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if (onfalse) BLTCTR(cr); else BGECTR(cr);
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break;
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default:
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@ -559,22 +547,26 @@ namespace nanojit
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CMPWI(cr, ra, d);
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return;
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}
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#if defined NANOJIT_64BIT
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if (condop >= LIR_qeq && condop <= LIR_qge) {
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CMPDI(cr, ra, d);
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TODO(cmpdi);
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return;
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}
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#endif
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}
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if (isU16(d)) {
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if ((condop == LIR_eq || condop >= LIR_ult && condop <= LIR_uge)) {
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CMPLWI(cr, ra, d);
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return;
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}
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#if defined NANOJIT_64BIT
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if ((condop == LIR_qeq || condop >= LIR_qult && condop <= LIR_quge)) {
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CMPLDI(cr, ra, d);
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TODO(cmpldi);
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return;
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}
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#endif
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}
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}
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#endif
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@ -583,14 +575,18 @@ namespace nanojit
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Register rb = b==a ? ra : findRegFor(b, allow & ~rmask(ra));
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if (condop >= LIR_eq && condop <= LIR_ge) {
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CMPW(cr, ra, rb);
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} else if (condop >= LIR_ult && condop <= LIR_uge) {
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}
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else if (condop >= LIR_ult && condop <= LIR_uge) {
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CMPLW(cr, ra, rb);
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} else if (condop >= LIR_qeq && condop <= LIR_qge) {
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}
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#if defined NANOJIT_64BIT
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else if (condop >= LIR_qeq && condop <= LIR_qge) {
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CMPD(cr, ra, rb);
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}
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else if (condop >= LIR_qult && condop <= LIR_quge) {
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CMPLD(cr, ra, rb);
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}
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#endif
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else if (condop >= LIR_feq && condop <= LIR_fge) {
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// set the lt/gt bit for fle/fge. We don't do this for
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// int/uint because in those cases we can invert the branch condition.
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@ -850,7 +846,7 @@ namespace nanojit
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// ppc arith immediate ops sign-exted the imm16 value
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switch (op) {
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case LIR_add:
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case LIR_iaddp:
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CASE32(LIR_iaddp:)
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CASE64(LIR_qiadd:)
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CASE64(LIR_qaddp:)
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ADDI(rr, ra, rhsc);
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@ -901,7 +897,7 @@ namespace nanojit
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CASE64(LIR_qiadd:)
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CASE64(LIR_qaddp:)
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case LIR_add:
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case LIR_iaddp:
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CASE32(LIR_iaddp:)
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ADD(rr, ra, rb);
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break;
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CASE64(LIR_qiand:)
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@ -1010,6 +1006,7 @@ namespace nanojit
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NanoAssertMsg(0, "NJ_F2I_SUPPORTED not yet supported for this architecture");
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}
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#if defined NANOJIT_64BIT
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// XXX: this is sub-optimal, see https://bugzilla.mozilla.org/show_bug.cgi?id=540368#c7.
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void Assembler::asm_q2i(LIns *ins) {
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Register rr = deprecated_prepResultReg(ins, GpRegs);
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@ -1033,7 +1030,8 @@ namespace nanojit
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break;
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}
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}
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#endif
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void Assembler::asm_quad(LIns *ins) {
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#ifdef NANOJIT_64BIT
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Register r = ins->deprecated_getReg();
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@ -1172,9 +1170,13 @@ namespace nanojit
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LIns* iffalse = ins->oprnd3();
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NanoAssert(cond->isCmp());
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#ifdef NANOJIT_64BIT
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NanoAssert((ins->opcode() == LIR_cmov && iftrue->isI32() && iffalse->isI32()) ||
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(ins->opcode() == LIR_qcmov && iftrue->isI64() && iffalse->isI64()));
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#else
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NanoAssert((ins->opcode() == LIR_cmov && iftrue->isI32() && iffalse->isI32()));
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#endif
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// fixme: we could handle fpu registers here, too, since we're just branching
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Register rr = deprecated_prepResultReg(ins, GpRegs);
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findSpecificRegFor(iftrue, rr);
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@ -1188,8 +1190,12 @@ namespace nanojit
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RegisterMask Assembler::hint(LIns* ins) {
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LOpcode op = ins->opcode();
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RegisterMask prefer = 0;
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if (op == LIR_icall || op == LIR_qcall)
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if (op == LIR_icall)
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prefer = rmask(R3);
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#ifdef NANOJIT_64BIT
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else if (op == LIR_qcall)
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prefer = rmask(R3);
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#endif
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else if (op == LIR_fcall)
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prefer = rmask(F1);
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else if (op == LIR_param) {
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