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Bug 965236 - ARM simulator: Add support for the udiv instruction. r=nbp
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@ -2931,9 +2931,9 @@ Simulator::decodeType3(SimInstruction *instr)
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break;
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break;
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}
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}
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case db_x: { // sudiv
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case db_x: { // sudiv
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if (instr->bit(22) == 0x0 && instr->bit(20) == 0x1 &&
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instr->bits(15,12) == 0x0f && instr->bits(7, 4) == 0x1) {
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if (!instr->hasW()) {
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if (!instr->hasW()) {
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if (instr->bits(5, 4) == 0x1) {
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if ((instr->bit(22) == 0x0) && (instr->bit(20) == 0x1)) {
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// sdiv (in V8 notation matching ARM ISA format) rn = rm/rs
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// sdiv (in V8 notation matching ARM ISA format) rn = rm/rs
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int rm = instr->rmValue();
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int rm = instr->rmValue();
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int32_t rm_val = get_register(rm);
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int32_t rm_val = get_register(rm);
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@ -2947,7 +2947,17 @@ Simulator::decodeType3(SimInstruction *instr)
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ret_val = rm_val / rs_val;
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ret_val = rm_val / rs_val;
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set_register(rn, ret_val);
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set_register(rn, ret_val);
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return;
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return;
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}
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} else {
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// udiv (in V8 notation matching ARM ISA format) rn = rm/rs
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int rm = instr->rmValue();
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uint32_t rm_val = get_register(rm);
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int rs = instr->rsValue();
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uint32_t rs_val = get_register(rs);
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uint32_t ret_val = 0;
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MOZ_ASSERT(rs_val != 0);
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ret_val = rm_val / rs_val;
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set_register(rn, ret_val);
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return;
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}
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}
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}
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}
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