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b=484561; [arm] fix EABI calling convention; clean up asm_call; r=graydon
This commit is contained in:
Vladimir Vukicevic
parent
34105fd15e
commit
eb82870ba4
@ -1943,12 +1943,6 @@ namespace nanojit
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for (uint32_t i = 0; i < MAXARGS; i++) {
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argt >>= 2;
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ArgSize a = ArgSize(argt&3);
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if (AvmCore::config.soft_float && a == ARGSIZE_F) {
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sizes[argc++] = ARGSIZE_LO;
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sizes[argc++] = ARGSIZE_LO;
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continue;
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}
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if (a != ARGSIZE_NONE) {
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sizes[argc++] = a;
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} else {
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@ -1100,28 +1100,12 @@ namespace nanojit
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LOpcode op = (ci->isIndirect() ? k_callimap : k_callmap)[argt & 3];
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NanoAssert(op != LIR_skip); // LIR_skip here is just an error condition
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ArgSize sizes[2*MAXARGS];
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ArgSize sizes[MAXARGS];
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int32_t argc = ci->get_sizes(sizes);
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if (AvmCore::config.soft_float) {
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if (op == LIR_fcall)
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op = LIR_callh;
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LInsp args2[MAXARGS*2]; // arm could require 2 args per double
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int32_t j = 0;
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int32_t i = 0;
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while (j < argc) {
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argt >>= 2;
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ArgSize a = ArgSize(argt&3);
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if (a == ARGSIZE_F) {
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LInsp q = args[i++];
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args2[j++] = ins1(LIR_qhi, q);
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args2[j++] = ins1(LIR_qlo, q);
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} else {
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args2[j++] = args[i++];
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}
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}
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args = args2;
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NanoAssert(j == argc);
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}
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//
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@ -54,6 +54,13 @@
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extern "C" void __clear_cache(char *BEG, char *END);
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#endif
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// assume EABI, except under CE
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#ifdef UNDER_CE
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#undef NJ_ARM_EABI
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#else
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#define NJ_ARM_EABI
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#endif
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#ifdef FEATURE_NANOJIT
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namespace nanojit
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@ -175,19 +182,162 @@ Assembler::genEpilogue()
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return _nIns;
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}
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/* ARM EABI (used by gcc/linux) calling conventions differ from Windows CE; use these
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* as the default.
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/* gcc/linux use the ARM EABI; Windows CE uses the legacy abi.
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*
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* - double arg following an initial dword arg use r0 for the int arg
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* and r2/r3 for the double; r1 is skipped
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* - 3 dword args followed by a double arg cause r3 to be skipped,
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* and the double to be stuck on the stack.
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* Under EABI:
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* - doubles are 64-bit aligned both in registers and on the stack.
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* If the next available argument register is R1, it is skipped
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* and the double is placed in R2:R3. If R0:R1 or R2:R3 are not
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* available, the double is placed on the stack, 64-bit aligned.
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* - 32-bit arguments are placed in registers and 32-bit aligned
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* on the stack.
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*
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* Under Windows CE, the arguments are placed in r0-r3 and then the stack,
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* one dword at a time, with the high order dword of a quad/double coming
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* first. No registers are skipped as they are in the EABI case.
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* Under legacy ABI:
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* - doubles are placed in subsequent arg registers; if the next
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* available register is r3, the low order word goes into r3
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* and the high order goes on the stack.
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* - 32-bit arguments are placed in the next available arg register,
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* - both doubles and 32-bit arguments are placed on stack with 32-bit
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* alignment.
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*/
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void
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Assembler::asm_arg(ArgSize sz, LInsp p, Register r)
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{
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// should never be called -- the ARM-specific longer form of
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// asm_arg is used on ARM.
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NanoAssert(0);
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}
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/*
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* asm_arg will update r and stkd to indicate where the next
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* argument should go. If r == UnknownReg, then the argument
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* is placed on the stack at stkd, and stkd is updated.
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*
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* Note that this currently doesn't actually use stkd on input,
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* except for figuring out alignment; it always pushes to SP.
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* See TODO in asm_call.
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*/
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void
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Assembler::asm_arg(ArgSize sz, LInsp arg, Register& r, int& stkd)
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{
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if (sz == ARGSIZE_F) {
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#ifdef NJ_ARM_EABI
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NanoAssert(r == UnknownReg || r == R0 || r == R2);
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// if we're about to put this on the stack, make sure the
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// stack is 64-bit aligned
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if (r == UnknownReg && (stkd&7) != 0) {
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SUBi(SP, SP, 4);
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stkd += 4;
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}
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#endif
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Reservation* argRes = getresv(arg);
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// handle qjoin first; won't ever show up if VFP is available
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if (arg->isop(LIR_qjoin)) {
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asm_arg(ARGSIZE_LO, arg->oprnd1(), r, stkd);
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asm_arg(ARGSIZE_LO, arg->oprnd2(), r, stkd);
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} else if (!argRes || argRes->reg == UnknownReg || !AvmCore::config.vfp) {
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// if we don't have a register allocated,
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// or we're not vfp, just read from memory.
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if (arg->isop(LIR_quad)) {
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const int32_t* p = (const int32_t*) (arg-2);
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// XXX use some load-multiple action here from our const pool?
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for (int k = 0; k < 2; k++) {
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if (r != UnknownReg) {
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asm_ld_imm(r, *p++);
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r = nextreg(r);
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if (r == R4)
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r = UnknownReg;
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} else {
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STR_preindex(IP, SP, -4);
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asm_ld_imm(IP, *p++);
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stkd += 4;
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}
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}
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} else {
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int d = findMemFor(arg);
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for (int k = 0; k < 2; k++) {
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if (r != UnknownReg) {
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LDR(r, FP, d + k*4);
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r = nextreg(r);
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if (r == R4)
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r = UnknownReg;
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} else {
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STR_preindex(IP, SP, -4);
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LDR(IP, FP, d + k*4);
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stkd += 4;
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}
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}
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}
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} else {
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// handle the VFP with-register case
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Register sr = argRes->reg;
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if (r != UnknownReg && r < R3) {
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FMRRD(r, nextreg(r), sr);
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// make sure the next register is correct on return
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if (r == R0)
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r = R2;
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else
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r = UnknownReg;
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} else if (r == R3) {
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// legacy ABI only
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STR_preindex(IP, SP, -4);
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FMRDL(IP, sr);
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FMRDH(r, sr);
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stkd += 4;
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r = UnknownReg;
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} else {
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FSTD(sr, SP, 0);
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SUB(SP, SP, 8);
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stkd += 8;
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r = UnknownReg;
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}
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}
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} else if (sz == ARGSIZE_LO) {
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if (r != UnknownReg) {
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if (arg->isconst()) {
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asm_ld_imm(r, arg->constval());
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} else {
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Reservation* argRes = getresv(arg);
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if (argRes) {
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if (argRes->reg == UnknownReg) {
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// load it into the arg reg
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int d = findMemFor(arg);
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if (arg->isop(LIR_alloc)) {
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asm_add_imm(r, FP, d);
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} else {
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LDR(r, FP, d);
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}
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} else {
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MOV(r, argRes->reg);
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}
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} else {
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findSpecificRegFor(arg, r);
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}
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}
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if (r < R3)
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r = nextreg(r);
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else
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r = UnknownReg;
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} else {
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int d = findMemFor(arg);
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STR_preindex(IP, SP, -4);
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LDR(IP, FP, d);
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stkd += 4;
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}
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} else {
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NanoAssert(0);
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}
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}
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void
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Assembler::asm_call(LInsp ins)
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{
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@ -202,30 +352,14 @@ Assembler::asm_call(LInsp ins)
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atypes >>= 2;
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bool arg0IsInt32FollowedByFloat = false;
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#ifndef UNDER_CE
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// we need to detect if we have arg0 as LO followed by arg1 as F;
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// in that case, we need to skip using r1 -- the F needs to be
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// loaded in r2/r3, at least according to the ARM EABI and gcc 4.2's
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// generated code.
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while ((atypes & 3) != ARGSIZE_NONE) {
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if (((atypes >> 2) & 3) == ARGSIZE_LO &&
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((atypes >> 0) & 3) == ARGSIZE_F &&
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((atypes >> 4) & 3) == ARGSIZE_NONE)
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{
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arg0IsInt32FollowedByFloat = true;
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break;
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}
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atypes >>= 2;
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}
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#endif
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// if we're using VFP, and the return type is a double,
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// it'll come back in R0/R1. We need to either place it
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// in the result fp reg, or store it.
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if (AvmCore::config.vfp && rsize == ARGSIZE_F) {
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NanoAssert(ins->opcode() == LIR_fcall);
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NanoAssert(callRes);
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//fprintf (stderr, "call ins: %p callRes: %p reg: %d ar: %d\n", ins, callRes, callRes->reg, callRes->arIndex);
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Register rr = callRes->reg;
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int d = disp(callRes);
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freeRsrcOf(ins, rr != UnknownReg);
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@ -240,50 +374,37 @@ Assembler::asm_call(LInsp ins)
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}
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}
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// make the call
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BL((NIns*)(call->_address));
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ArgSize sizes[10];
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ArgSize sizes[MAXARGS];
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uint32_t argc = call->get_sizes(sizes);
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Register r = R0;
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int stkd = 0;
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// XXX TODO we should go through the args and figure out how much
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// stack space we'll need, allocate it up front, and then do
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// SP-relative stores using stkd instead of doing STR_preindex for
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// every stack write like we currently do in asm_arg.
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for(uint32_t i = 0; i < argc; i++) {
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uint32_t j = argc - i - 1;
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ArgSize sz = sizes[j];
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LInsp arg = ins->arg(j);
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// pre-assign registers R0-R3 for arguments (if they fit)
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Register r = (i + roffset) < 4 ? argRegs[i+roffset] : UnknownReg;
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NanoAssert(r < R4 || r == UnknownReg);
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#ifdef NJ_ARM_EABI
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if (sz == ARGSIZE_F) {
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Register rlo = UnknownReg;
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Register rhi = UnknownReg;
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#ifdef UNDER_CE
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if (r >= R0 && r <= R2) {
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rlo = r;
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rhi = nextreg(r);
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roffset++;
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} else if (r == R3) {
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rlo = r;
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rhi = UnknownReg;
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}
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#else
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if (r == R0 || r == R2) {
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rlo = r;
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rhi = nextreg(r);
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roffset++;
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} else if (r == R1) {
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rlo = R2;
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rhi = nextreg(r);
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roffset += 2;
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}
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if (r == R1)
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r = R2;
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else if (r == R3)
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r = UnknownReg;
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}
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#endif
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asm_arm_farg(arg, rlo, rhi);
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} else {
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asm_arg(sz, arg, r);
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}
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// Under CE, arg0IsInt32FollowedByFloat will always be false
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if (i == 0 && arg0IsInt32FollowedByFloat)
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roffset = 1;
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asm_arg(sz, arg, r, stkd);
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}
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}
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@ -1612,132 +1733,6 @@ Assembler::asm_int(LInsp ins)
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LDi(rr, val);
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}
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void
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Assembler::asm_pusharg(LInsp arg)
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{
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Reservation* argRes = getresv(arg);
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bool quad = arg->isQuad();
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if (argRes && argRes->reg != UnknownReg) {
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if (!quad) {
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STR_preindex(argRes->reg, SP, -4);
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} else {
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FSTD(argRes->reg, SP, 0);
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SUBi(SP, SP, 8);
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}
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} else {
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int d = findMemFor(arg);
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if (!quad) {
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STR_preindex(IP, SP, -4);
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LDR(IP, FP, d);
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} else {
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STR_preindex(IP, SP, -4);
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LDR(IP, FP, d+4);
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STR_preindex(IP, SP, -4);
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LDR(IP, FP, d);
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}
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}
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}
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void
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Assembler::asm_arg(ArgSize sz, LInsp p, Register r)
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{
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// this only handles ARGSIZE_LO; we don't support ARGSIZE_Q,
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// and ARGSIZE_F is handled by asm_arm_farg
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NanoAssert(sz == ARGSIZE_LO);
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if (r != UnknownReg) {
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// arg goes in specific register
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if (p->isconst()) {
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LDi(r, p->constval());
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} else {
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Reservation* rA = getresv(p);
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if (rA) {
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if (rA->reg == UnknownReg) {
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// load it into the arg reg
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int d = findMemFor(p);
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if (p->isop(LIR_alloc)) {
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asm_add_imm(r, FP, d);
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} else {
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LDR(r, FP, d);
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}
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} else {
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// it must be in a saved reg
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MOV(r, rA->reg);
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}
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} else {
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// this is the last use, so fine to assign it
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// to the scratch reg, it's dead after this point.
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findSpecificRegFor(p, r);
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}
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}
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} else {
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asm_pusharg(p);
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}
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}
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void
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Assembler::asm_arm_farg(LInsp arg, Register rlo, Register rhi)
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{
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if (AvmCore::config.vfp) {
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Register sr = findRegFor(arg, FpRegs);
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if (rlo != UnknownReg && rhi != UnknownReg) {
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NanoAssert(sr != UnknownReg);
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FMRRD(rlo, rhi, sr);
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} else if (rlo != UnknownReg && rhi == UnknownReg) {
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NanoAssert(sr != UnknownReg);
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STR_preindex(IP, SP, -4);
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FMRDL(IP, sr);
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FMRDH(rhi, sr);
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} else {
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asm_pusharg(arg);
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}
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return;
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}
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NanoAssert(arg->opcode() == LIR_qjoin || arg->opcode() == LIR_quad);
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if (rlo != UnknownReg && rhi != UnknownReg) {
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if (arg->opcode() == LIR_qjoin) {
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LIns* lo = arg->oprnd1();
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LIns* hi = arg->oprnd2();
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findSpecificRegFor(lo, rlo);
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findSpecificRegFor(hi, rhi);
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} else {
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// LIR_quad
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const int32_t* p = (const int32_t*) (arg-2);
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asm_ld_imm(rhi, p[1]);
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asm_ld_imm(rlo, p[0]);
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}
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} else if (rlo != UnknownReg && rhi == UnknownReg) {
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if (arg->opcode() == LIR_qjoin) {
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LIns* lo = arg->oprnd1();
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LIns* hi = arg->oprnd2();
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int d = findMemFor(hi);
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findSpecificRegFor(lo, rlo);
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STR_preindex(IP, SP, -4);
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LDR(IP, FP, d);
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} else {
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// LIR_quad
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const int32_t* p = (const int32_t*) (arg-2);
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STR_preindex(IP, SP, -4);
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asm_ld_imm(IP, p[1]);
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asm_ld_imm(rlo, p[0]);
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}
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} else {
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asm_pusharg(arg);
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}
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}
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}
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#endif /* FEATURE_NANOJIT */
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@ -192,7 +192,7 @@ verbose_only( extern const char* shiftNames[]; )
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void asm_cmpi(Register, int32_t imm); \
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void asm_ldr_chk(Register d, Register b, int32_t off, bool chk); \
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void asm_ld_imm(Register d, int32_t imm); \
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void asm_arm_farg(LInsp arg, Register rlo, Register rhi); \
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void asm_arg(ArgSize sz, LInsp arg, Register& r, int& stkd); \
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int* _nSlot; \
|
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int* _nExitSlot;
|
||||
|
||||
@ -521,7 +521,7 @@ enum {
|
||||
underrunProtect(4); \
|
||||
if ((_off)<0) *(--_nIns) = (NIns)( COND_AL | (0x52<<20) | ((_n)<<16) | ((_d)<<12) | ((-(_off))&0xFFF) ); \
|
||||
else *(--_nIns) = (NIns)( COND_AL | (0x5A<<20) | ((_n)<<16) | ((_d)<<12) | ((_off)&0xFFF) ); \
|
||||
asm_output("str %s, [%s, #%d]", gpn(_d), gpn(_n), (_off)); \
|
||||
asm_output("str %s, [%s, #%d]!", gpn(_d), gpn(_n), (_off)); \
|
||||
} while(0)
|
||||
|
||||
// [Rd] = Rn ; Rd += _off
|
||||
@ -530,7 +530,7 @@ enum {
|
||||
underrunProtect(4); \
|
||||
if ((_off)<0) *(--_nIns) = (NIns)( COND_AL | (0x40<<20) | ((_n)<<16) | ((_d)<<12) | ((-(_off))&0xFFF) ); \
|
||||
else *(--_nIns) = (NIns)( COND_AL | (0x48<<20) | ((_n)<<16) | ((_d)<<12) | ((_off)&0xFFF) ); \
|
||||
asm_output("str %s, [%s], %d", gpn(_d), gpn(_n), (_off)); \
|
||||
asm_output("str %s, [%s]!, %d", gpn(_d), gpn(_n), (_off)); \
|
||||
} while(0)
|
||||
|
||||
//#define RET() underrunProtect(1); *(--_nIns) = 0xc3; asm_output("ret")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user