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[JAEGER] Fix ARM's long-range loads. [No bug] [r=me]

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This commit is contained in:
Jacob Bramley 2010-08-17 15:19:31 +01:00
parent 3379e781d1
commit d09759c622
2 changed files with 12 additions and 12 deletions
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16
js/src/assembler/assembler/ARMAssembler.cpp
View File

@ -275,8 +275,8 @@ void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID bas
add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtr_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtr_ur(isLoad, srcDst, base, reg);
moveImm(offset, ARMRegisters::S0);
dtr_ur(isLoad, srcDst, base, ARMRegisters::S0);
}
} else {
offset = -offset;
@ -286,8 +286,8 @@ void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID bas
sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtr_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtr_dr(isLoad, srcDst, base, reg);
moveImm(offset, ARMRegisters::S0);
dtr_dr(isLoad, srcDst, base, ARMRegisters::S0);
}
}
}
@ -301,8 +301,8 @@ void ARMAssembler::dataTransfer8(bool isLoad, RegisterID srcDst, RegisterID base
add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtrb_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtrb_ur(isLoad, srcDst, base, reg);
moveImm(offset, ARMRegisters::S0);
dtrb_ur(isLoad, srcDst, base, ARMRegisters::S0);
}
} else {
offset = -offset;
@ -312,8 +312,8 @@ void ARMAssembler::dataTransfer8(bool isLoad, RegisterID srcDst, RegisterID base
sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtrb_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtrb_dr(isLoad, srcDst, base, reg);
moveImm(offset, ARMRegisters::S0);
dtrb_dr(isLoad, srcDst, base, ARMRegisters::S0);
}
}
}

8
js/src/assembler/assembler/MacroAssemblerARM.h
View File

@ -1116,8 +1116,8 @@ protected:
m_assembler.add_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
m_assembler.dtr_u(true, ARMRegisters::S0, ARMRegisters::S0, offset & 0xfff);
} else {
ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
m_assembler.dtr_ur(true, ARMRegisters::S0, base, reg);
m_assembler.moveImm(offset, ARMRegisters::S0);
m_assembler.dtr_ur(true, ARMRegisters::S0, base, ARMRegisters::S0);
}
} else {
offset = -offset;
@ -1127,8 +1127,8 @@ protected:
m_assembler.sub_r(ARMRegisters::S0, base, ARMAssembler::OP2_IMM | (offset >> 12) | (10 << 8));
m_assembler.dtr_d(true, ARMRegisters::S0, ARMRegisters::S0, offset & 0xfff);
} else {
ARMWord reg = m_assembler.getImm(offset, ARMRegisters::S0);
m_assembler.dtr_dr(true, ARMRegisters::S0, base, reg);
m_assembler.moveImm(offset, ARMRegisters::S0);
m_assembler.dtr_dr(true, ARMRegisters::S0, base, ARMRegisters::S0);
}
}
m_assembler.blx(ARMRegisters::S0);