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Bug 1019831: SIMD x86-x64: Int32x4 unaligned moves; r=sunfish

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--HG--
extra : rebase_source : a3b4ccfced4d5fa6ab141cf317a45f08fac8eda4
This commit is contained in:
Benjamin Bouvier 2014-08-07 17:58:24 +02:00
parent f54a24e8e7
commit cb1120c330
3 changed files with 64 additions and 0 deletions
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32
js/src/assembler/assembler/X86Assembler.h
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@ -2875,6 +2875,38 @@ public:
m_formatter.twoByteOp(OP2_MOVAPD_VsdWsd, (RegisterID)dst, (RegisterID)src);
}
void movdqu_rm(XMMRegisterID src, int offset, RegisterID base)
{
spew("movdqu %s, %s0x%x(%s)",
nameFPReg(src), PRETTY_PRINT_OFFSET(offset), nameIReg(base));
m_formatter.prefix(PRE_SSE_F3);
m_formatter.twoByteOp(OP2_MOVDQ_WdqVdq, (RegisterID)src, base, offset);
}
void movdqu_rm(XMMRegisterID src, int offset, RegisterID base, RegisterID index, int scale)
{
spew("movdqu %s, %d(%s,%s,%d)",
nameFPReg(src), offset, nameIReg(base), nameIReg(index), 1<<scale);
m_formatter.prefix(PRE_SSE_F3);
m_formatter.twoByteOp(OP2_MOVDQ_WdqVdq, (RegisterID)src, base, index, scale, offset);
}
void movdqu_mr(int offset, RegisterID base, XMMRegisterID dst)
{
spew("movdqu %s0x%x(%s), %s",
PRETTY_PRINT_OFFSET(offset), nameIReg(base), nameFPReg(dst));
m_formatter.prefix(PRE_SSE_F3);
m_formatter.twoByteOp(OP2_MOVDQ_VdqWdq, (RegisterID)dst, base, offset);
}
void movdqu_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
{
spew("movdqu %d(%s,%s,%d), %s",
offset, nameIReg(base), nameIReg(index), 1<<scale, nameFPReg(dst));
m_formatter.prefix(PRE_SSE_F3);
m_formatter.twoByteOp(OP2_MOVDQ_VdqWdq, (RegisterID)dst, base, index, scale, offset);
}
void movdqa_rr(XMMRegisterID src, XMMRegisterID dst)
{
spew("movdqa %s, %s",

26
js/src/jit/shared/Assembler-x86-shared.h
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@ -467,6 +467,32 @@ class AssemblerX86Shared : public AssemblerShared
void movss(FloatRegister src, const BaseIndex &dest) {
masm.movss_rm(src.code(), dest.offset, dest.base.code(), dest.index.code(), dest.scale);
}
void movdqu(const Operand &src, FloatRegister dest) {
JS_ASSERT(HasSSE2());
switch (src.kind()) {
case Operand::MEM_REG_DISP:
masm.movdqu_mr(src.disp(), src.base(), dest.code());
break;
case Operand::MEM_SCALE:
masm.movdqu_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
break;
default:
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void movdqu(FloatRegister src, const Operand &dest) {
JS_ASSERT(HasSSE2());
switch (dest.kind()) {
case Operand::MEM_REG_DISP:
masm.movdqu_rm(src.code(), dest.disp(), dest.base());
break;
case Operand::MEM_SCALE:
masm.movdqu_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
break;
default:
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void movdqa(const Operand &src, FloatRegister dest) {
JS_ASSERT(HasSSE2());
switch (src.kind()) {

6
js/src/jit/shared/MacroAssembler-x86-shared.h
View File

@ -476,6 +476,12 @@ class MacroAssemblerX86Shared : public Assembler
void moveAlignedInt32x4(FloatRegister src, FloatRegister dest) {
movdqa(src, dest);
}
void loadUnalignedInt32x4(const Address &src, FloatRegister dest) {
movdqu(Operand(src), dest);
}
void storeUnalignedInt32x4(FloatRegister src, const Address &dest) {
movdqu(src, Operand(dest));
}
void loadAlignedFloat32x4(const Address &src, FloatRegister dest) {
movaps(Operand(src), dest);