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[JAEGER] Fix ARM's load8 implementation and enable YARR for ARM. [Bug 564953] [r=me]

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This commit is contained in:
Jacob Bramley 2010-08-16 13:20:32 +01:00
parent bcd9f334be
commit becdbf3574
4 changed files with 82 additions and 11 deletions
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41
js/src/assembler/assembler/ARMAssembler.cpp
View File

@ -266,29 +266,54 @@ ARMWord ARMAssembler::encodeComplexImm(ARMWord imm, int dest)
// Memory load/store helpers
void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset, bool bytes)
void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset)
{
ARMWord transferFlag = bytes ? DT_BYTE : 0;
if (offset >= 0) {
if (offset <= 0xfff)
dtr_u(isLoad, srcDst, base, offset | transferFlag);
dtr_u(isLoad, srcDst, base, offset);
else if (offset <= 0xfffff) {
add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtr_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
dtr_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtr_ur(isLoad, srcDst, base, reg | transferFlag);
dtr_ur(isLoad, srcDst, base, reg);
}
} else {
offset = -offset;
if (offset <= 0xfff)
dtr_d(isLoad, srcDst, base, offset | transferFlag);
dtr_d(isLoad, srcDst, base, offset);
else if (offset <= 0xfffff) {
sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtr_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
dtr_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtr_dr(isLoad, srcDst, base, reg | transferFlag);
dtr_dr(isLoad, srcDst, base, reg);
}
}
}
void ARMAssembler::dataTransfer8(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset)
{
if (offset >= 0) {
if (offset <= 0xfff)
dtrb_u(isLoad, srcDst, base, offset);
else if (offset <= 0xfffff) {
add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtrb_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtrb_ur(isLoad, srcDst, base, reg);
}
} else {
offset = -offset;
if (offset <= 0xfff)
dtrb_d(isLoad, srcDst, base, offset);
else if (offset <= 0xfffff) {
sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
dtrb_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff));
} else {
ARMWord reg = getImm(offset, ARMRegisters::S0);
dtrb_dr(isLoad, srcDst, base, reg);
}
}
}

47
js/src/assembler/assembler/ARMAssembler.h
View File

@ -654,6 +654,50 @@ namespace JSC {
emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm);
}
// Data transfers like this:
// LDRB rd, [rb, +offset]
// STRB rd, [rb, +offset]
void dtrb_u(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #+%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, offset);
}
// Data transfers like this:
// LDRB rd, [rb, +rm]
// STRB rd, [rb, +rm]
void dtrb_ur(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, +%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | DT_UP | OP2_OFSREG, rd, rb, rm);
}
// Data transfers like this:
// LDRB rd, [rb, -offset]
// STRB rd, [rb, -offset]
void dtrb_d(bool isLoad, int rd, int rb, ARMWord offset, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, #-%u]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), offset);
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0), rd, rb, offset);
}
// Data transfers like this:
// LDRB rd, [rb, -rm]
// STRB rd, [rb, -rm]
void dtrb_dr(bool isLoad, int rd, int rb, int rm, Condition cc = AL)
{
char const * mnemonic = (isLoad) ? ("ldrb") : ("strb");
js::JaegerSpew(js::JSpew_Insns,
IPFX "%-15s %s, [%s, -%s]\n", MAYBE_PAD, mnemonic, nameGpReg(rd), nameGpReg(rb), nameGpReg(rm));
emitInst(static_cast<ARMWord>(cc) | DTR | DT_BYTE | (isLoad ? DT_LOAD : 0) | OP2_OFSREG, rd, rb, rm);
}
void ldrh_r(int rd, int rb, int rm, Condition cc = AL)
{
js::JaegerSpew(js::JSpew_Insns,
@ -1125,7 +1169,8 @@ namespace JSC {
// Memory load/store helpers
void dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset, bool bytes = false);
void dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset);
void dataTransfer8(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset);
void baseIndexTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset);
void doubleTransfer(bool isLoad, FPRegisterID srcDst, RegisterID base, int32_t offset);

2
js/src/assembler/assembler/MacroAssemblerARM.h
View File

@ -253,7 +253,7 @@ public:
void load8(ImplicitAddress address, RegisterID dest)
{
m_assembler.dataTransfer32(true, dest, address.base, address.offset, true);
m_assembler.dataTransfer8(true, dest, address.base, address.offset);
}
void load32(ImplicitAddress address, RegisterID dest)

3
js/src/assembler/wtf/Platform.h
View File

@ -893,10 +893,11 @@ on MinGW. See https://bugs.webkit.org/show_bug.cgi?id=29268 */
/* Yet Another Regex Runtime. */
#if !defined(ENABLE_YARR_JIT)
/* YARR supports x86 & x86-64, and has been tested on Mac and Windows. */
/* YARR supports ARM, x86 & x86-64, and has been tested on Mac and Windows. */
#if WTF_CPU_X86 \
|| WTF_CPU_X86_64 \
|| WTF_CPU_ARM_THUMB2 \
|| WTF_CPU_ARM_TRADITIONAL \
|| WTF_CPU_X86
#define ENABLE_YARR_JIT 1
#else