Bug 977126 Part 2 -- Changes to x86/x64 to support subPtr(Register,Address) r=jandem

This commit is contained in:
Nicholas D. Matsakis 2014-03-20 10:03:57 -04:00
parent 60e315db7c
commit b766546539
5 changed files with 37 additions and 0 deletions

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@ -942,6 +942,13 @@ public:
m_formatter.oneByteOp64(OP_SUB_EvGv, src, dst);
}
void subq_rm(RegisterID src, int offset, RegisterID base)
{
spew("subq %s, %s0x%x(%s)",
nameIReg(8,src), PRETTY_PRINT_OFFSET(offset), nameIReg(8,base));
m_formatter.oneByteOp64(OP_SUB_EvGv, src, base, offset);
}
void subq_mr(int offset, RegisterID base, RegisterID dst)
{
spew("subq %s0x%x(%s), %s",

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@ -948,6 +948,18 @@ class AssemblerX86Shared
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void subl(const Register &src, const Operand &dest) {
switch (dest.kind()) {
case Operand::REG:
masm.subl_rr(src.code(), dest.reg());
break;
case Operand::MEM_REG_DISP:
masm.subl_rm(src.code(), dest.disp(), dest.base());
break;
default:
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void orl(const Register &reg, const Register &dest) {
masm.orl_rr(reg.code(), dest.code());
}

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@ -449,6 +449,18 @@ class Assembler : public AssemblerX86Shared
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void subq(const Register &src, const Operand &dest) {
switch (dest.kind()) {
case Operand::REG:
masm.subq_rr(src.code(), dest.reg());
break;
case Operand::MEM_REG_DISP:
masm.subq_rm(src.code(), dest.disp(), dest.base());
break;
default:
MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
}
}
void shlq(Imm32 imm, const Register &dest) {
masm.shlq_i8r(imm.value, dest.code());
}

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@ -554,6 +554,9 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
void subPtr(const Address &addr, const Register &dest) {
subq(Operand(addr), dest);
}
void subPtr(const Register &src, const Address &dest) {
subq(src, Operand(dest));
}
void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
if (JSC::X86Assembler::isAddressImmediate(lhs.addr)) {

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@ -561,6 +561,9 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
void subPtr(const Address &addr, const Register &dest) {
subl(Operand(addr), dest);
}
void subPtr(const Register &src, const Address &dest) {
subl(src, Operand(dest));
}
void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
cmpl(Operand(lhs), rhs);