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Bug 977126 Part 2 -- Changes to x86/x64 to support subPtr(Register,Address) r=jandem
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@ -942,6 +942,13 @@ public:
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m_formatter.oneByteOp64(OP_SUB_EvGv, src, dst);
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}
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void subq_rm(RegisterID src, int offset, RegisterID base)
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{
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spew("subq %s, %s0x%x(%s)",
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nameIReg(8,src), PRETTY_PRINT_OFFSET(offset), nameIReg(8,base));
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m_formatter.oneByteOp64(OP_SUB_EvGv, src, base, offset);
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}
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void subq_mr(int offset, RegisterID base, RegisterID dst)
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{
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spew("subq %s0x%x(%s), %s",
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@ -948,6 +948,18 @@ class AssemblerX86Shared
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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}
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void subl(const Register &src, const Operand &dest) {
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switch (dest.kind()) {
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case Operand::REG:
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masm.subl_rr(src.code(), dest.reg());
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break;
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case Operand::MEM_REG_DISP:
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masm.subl_rm(src.code(), dest.disp(), dest.base());
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break;
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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}
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void orl(const Register ®, const Register &dest) {
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masm.orl_rr(reg.code(), dest.code());
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}
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@ -449,6 +449,18 @@ class Assembler : public AssemblerX86Shared
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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}
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void subq(const Register &src, const Operand &dest) {
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switch (dest.kind()) {
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case Operand::REG:
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masm.subq_rr(src.code(), dest.reg());
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break;
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case Operand::MEM_REG_DISP:
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masm.subq_rm(src.code(), dest.disp(), dest.base());
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break;
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default:
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MOZ_ASSUME_UNREACHABLE("unexpected operand kind");
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}
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}
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void shlq(Imm32 imm, const Register &dest) {
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masm.shlq_i8r(imm.value, dest.code());
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}
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@ -554,6 +554,9 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
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void subPtr(const Address &addr, const Register &dest) {
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subq(Operand(addr), dest);
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}
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void subPtr(const Register &src, const Address &dest) {
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subq(src, Operand(dest));
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}
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void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
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if (JSC::X86Assembler::isAddressImmediate(lhs.addr)) {
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@ -561,6 +561,9 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
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void subPtr(const Address &addr, const Register &dest) {
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subl(Operand(addr), dest);
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}
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void subPtr(const Register &src, const Address &dest) {
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subl(src, Operand(dest));
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}
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void branch32(Condition cond, const AbsoluteAddress &lhs, Imm32 rhs, Label *label) {
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cmpl(Operand(lhs), rhs);
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