diff --git a/js/src/jit/shared/Assembler-x86-shared.h b/js/src/jit/shared/Assembler-x86-shared.h
index 1cb8b015d08..55b247198f4 100644
--- a/js/src/jit/shared/Assembler-x86-shared.h
+++ b/js/src/jit/shared/Assembler-x86-shared.h
@@ -242,14 +242,14 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.movl_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movl_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.movl_mr(src.address(), dest.code());
             break;
 #endif
@@ -262,14 +262,14 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.movl_rr(src.code(), dest.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movl_rm(src.code(), dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movl_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.movl_rm(src.code(), dest.address());
             break;
 #endif
@@ -282,10 +282,10 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.movl_i32r(imm32.value, dest.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movl_i32m(imm32.value, dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movl_i32m(imm32.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -307,10 +307,10 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.movsd_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movsd_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movsd_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -323,10 +323,10 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.movsd_rr(src.code(), dest.fpu());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movsd_rm(src.code(), dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movsd_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -339,10 +339,10 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.movss_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movss_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movss_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -355,10 +355,10 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.movss_rr(src.code(), dest.fpu());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movss_rm(src.code(), dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movss_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -368,10 +368,10 @@ class AssemblerX86Shared
     void movdqa(const Operand &src, const FloatRegister &dest) {
         JS_ASSERT(HasSSE2());
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movdqa_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movdqa_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -381,10 +381,10 @@ class AssemblerX86Shared
     void movdqa(const FloatRegister &src, const Operand &dest) {
         JS_ASSERT(HasSSE2());
         switch (dest.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movdqa_rm(src.code(), dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movdqa_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -401,10 +401,10 @@ class AssemblerX86Shared
     }
     void movzbl(const Operand &src, const Register &dest) {
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movzbl_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movzbl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -413,10 +413,10 @@ class AssemblerX86Shared
     }
     void movsbl(const Operand &src, const Register &dest) {
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movsbl_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movsbl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -425,10 +425,10 @@ class AssemblerX86Shared
     }
     void movb(const Register &src, const Operand &dest) {
         switch (dest.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movb_rm(src.code(), dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movb_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -437,10 +437,10 @@ class AssemblerX86Shared
     }
     void movb(const Imm32 &src, const Operand &dest) {
         switch (dest.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movb_i8m(src.value, dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movb_i8m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -449,10 +449,10 @@ class AssemblerX86Shared
     }
     void movzwl(const Operand &src, const Register &dest) {
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movzwl_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movzwl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -462,10 +462,10 @@ class AssemblerX86Shared
 
     void movw(const Register &src, const Operand &dest) {
         switch (dest.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movw_rm(src.code(), dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movw_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -474,10 +474,10 @@ class AssemblerX86Shared
     }
     void movw(const Imm32 &src, const Operand &dest) {
         switch (dest.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movw_i16m(src.value, dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movw_i16m(src.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -486,10 +486,10 @@ class AssemblerX86Shared
     }
     void movswl(const Operand &src, const Register &dest) {
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movswl_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movswl_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -498,10 +498,10 @@ class AssemblerX86Shared
     }
     void leal(const Operand &src, const Register &dest) {
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.leal_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.leal_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -580,10 +580,10 @@ class AssemblerX86Shared
 
     void jmp(const Operand &op){
         switch (op.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.jmp_m(op.disp(), op.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.jmp_m(op.disp(), op.base(), op.index(), op.scale());
             break;
           case Operand::REG:
@@ -683,7 +683,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.call(op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.call_m(op.disp(), op.base());
             break;
           default:
@@ -716,7 +716,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.cmpl_rr(rhs.reg(), lhs.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpl_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
           default:
@@ -731,14 +731,14 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.cmpl_ir(imm.value, op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpl_im(imm.value, op.disp(), op.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.cmpl_im(imm.value, op.disp(), op.base(), op.index(), op.scale());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.cmpl_im(imm.value, op.address());
             break;
 #endif
@@ -751,11 +751,11 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.cmpl_rr(rhs.code(), lhs.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpl_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.cmpl_rm(rhs.code(), lhs.address());
             break;
 #endif
@@ -768,11 +768,11 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.cmpl_ir(imm.value, op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpl_im(imm.value, op.disp(), op.base());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.cmpl_im(imm.value, op.address());
             break;
 #endif
@@ -802,7 +802,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.testl_i32r(rhs.value, lhs.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.testl_i32m(rhs.value, lhs.disp(), lhs.base());
             break;
           default:
@@ -819,11 +819,11 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.addl_ir(imm.value, op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.addl_im(imm.value, op.disp(), op.base());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.addl_im(imm.value, op.address());
             break;
 #endif
@@ -839,7 +839,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.subl_ir(imm.value, op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.subl_im(imm.value, op.disp(), op.base());
             break;
           default:
@@ -857,7 +857,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.subl_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.subl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -875,7 +875,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.orl_ir(imm.value, op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.orl_im(imm.value, op.disp(), op.base());
             break;
           default:
@@ -893,7 +893,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.xorl_ir(imm.value, op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.xorl_im(imm.value, op.disp(), op.base());
             break;
           default:
@@ -911,7 +911,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.andl_ir(imm.value, op.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.andl_im(imm.value, op.disp(), op.base());
             break;
           default:
@@ -923,7 +923,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.addl_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.addl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -935,7 +935,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.orl_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.orl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -947,7 +947,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.xorl_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.xorl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -959,7 +959,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.andl_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.andl_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -977,7 +977,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.imull_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.imull_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -989,7 +989,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.negl_r(src.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.negl_m(src.disp(), src.base());
             break;
           default:
@@ -1004,7 +1004,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.notl_r(src.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.notl_m(src.disp(), src.base());
             break;
           default:
@@ -1042,7 +1042,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.push_r(src.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.push_m(src.disp(), src.base());
             break;
           default:
@@ -1058,7 +1058,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.pop_r(src.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.pop_m(src.disp(), src.base());
             break;
           default:
@@ -1114,7 +1114,7 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.pinsrd_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.pinsrd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1140,10 +1140,10 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.cvtsi2sd_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cvtsi2sd_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.cvtsi2sd_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -1164,10 +1164,10 @@ class AssemblerX86Shared
           case Operand::REG:
             masm.cvtsi2ss_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cvtsi2ss_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.cvtsi2ss_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -1224,11 +1224,11 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.addsd_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.addsd_mr(src.disp(), src.base(), dest.code());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.addsd_mr(src.address(), dest.code());
             break;
 #endif
@@ -1242,11 +1242,11 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.addss_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.addss_mr(src.disp(), src.base(), dest.code());
             break;
 #ifdef JS_CPU_X86
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.addss_mr(src.address(), dest.code());
             break;
 #endif
@@ -1268,7 +1268,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.subsd_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.subsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1281,7 +1281,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.subss_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.subss_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1298,7 +1298,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.mulsd_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.mulsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1311,7 +1311,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.mulss_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.mulss_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1336,7 +1336,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.divsd_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.divsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1349,7 +1349,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.divss_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.divss_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1392,7 +1392,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.minsd_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.minsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1409,7 +1409,7 @@ class AssemblerX86Shared
           case Operand::FPREG:
             masm.maxsd_rr(src.fpu(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.maxsd_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -1419,7 +1419,7 @@ class AssemblerX86Shared
     void fisttp(const Operand &dest) {
         JS_ASSERT(HasSSE3());
         switch (dest.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.fisttp_m(dest.disp(), dest.base());
             break;
           default:
@@ -1428,7 +1428,7 @@ class AssemblerX86Shared
     }
     void fld(const Operand &dest) {
         switch (dest.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.fld_m(dest.disp(), dest.base());
             break;
           default:
@@ -1437,7 +1437,7 @@ class AssemblerX86Shared
     }
     void fstp(const Operand &src) {
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.fstp_m(src.disp(), src.base());
             break;
           default:
diff --git a/js/src/jit/x64/Assembler-x64.h b/js/src/jit/x64/Assembler-x64.h
index 7c386fd619c..9f30950a464 100644
--- a/js/src/jit/x64/Assembler-x64.h
+++ b/js/src/jit/x64/Assembler-x64.h
@@ -173,9 +173,9 @@ class Operand
   public:
     enum Kind {
         REG,
-        REG_DISP,
+        MEM_REG_DISP,
         FPREG,
-        SCALE
+        MEM_SCALE
     };
 
     Kind kind_ : 3;
@@ -194,37 +194,37 @@ class Operand
         base_(reg.code())
     { }
     explicit Operand(const Address &address)
-      : kind_(REG_DISP),
+      : kind_(MEM_REG_DISP),
         base_(address.base.code()),
         disp_(address.offset)
     { }
     explicit Operand(const BaseIndex &address)
-      : kind_(SCALE),
+      : kind_(MEM_SCALE),
         base_(address.base.code()),
         scale_(address.scale),
         index_(address.index.code()),
         disp_(address.offset)
     { }
     Operand(Register base, Register index, Scale scale, int32_t disp = 0)
-      : kind_(SCALE),
+      : kind_(MEM_SCALE),
         base_(base.code()),
         scale_(scale),
         index_(index.code()),
         disp_(disp)
     { }
     Operand(Register reg, int32_t disp)
-      : kind_(REG_DISP),
+      : kind_(MEM_REG_DISP),
         base_(reg.code()),
         disp_(disp)
     { }
 
     Address toAddress() const {
-        JS_ASSERT(kind() == REG_DISP);
+        JS_ASSERT(kind() == MEM_REG_DISP);
         return Address(Register::FromCode(base()), disp());
     }
 
     BaseIndex toBaseIndex() const {
-        JS_ASSERT(kind() == SCALE);
+        JS_ASSERT(kind() == MEM_SCALE);
         return BaseIndex(Register::FromCode(base()), Register::FromCode(index()), scale(), disp());
     }
 
@@ -236,15 +236,15 @@ class Operand
         return (Registers::Code)base_;
     }
     Registers::Code base() const {
-        JS_ASSERT(kind() == REG_DISP || kind() == SCALE);
+        JS_ASSERT(kind() == MEM_REG_DISP || kind() == MEM_SCALE);
         return (Registers::Code)base_;
     }
     Registers::Code index() const {
-        JS_ASSERT(kind() == SCALE);
+        JS_ASSERT(kind() == MEM_SCALE);
         return (Registers::Code)index_;
     }
     Scale scale() const {
-        JS_ASSERT(kind() == SCALE);
+        JS_ASSERT(kind() == MEM_SCALE);
         return scale_;
     }
     FloatRegisters::Code fpu() const {
@@ -252,7 +252,7 @@ class Operand
         return (FloatRegisters::Code)base_;
     }
     int32_t disp() const {
-        JS_ASSERT(kind() == REG_DISP || kind() == SCALE);
+        JS_ASSERT(kind() == MEM_REG_DISP || kind() == MEM_SCALE);
         return disp_;
     }
 };
@@ -403,10 +403,10 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.movq_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movq_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -418,10 +418,10 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.movq_rr(src.code(), dest.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movq_rm(src.code(), dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movq_rm(src.code(), dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -433,10 +433,10 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.movl_i32r(imm32.value, dest.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movq_i32m(imm32.value, dest.disp(), dest.base());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movq_i32m(imm32.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             break;
           default:
@@ -472,7 +472,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.addq_ir(imm.value, dest.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.addq_im(imm.value, dest.disp(), dest.base());
             break;
           default:
@@ -487,7 +487,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.addq_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.addq_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -506,7 +506,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.subq_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.subq_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -533,7 +533,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.orq_rr(src.reg(), dest.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.orq_mr(src.disp(), src.base(), dest.code());
             break;
           default:
@@ -580,10 +580,10 @@ class Assembler : public AssemblerX86Shared
     }
     void lea(const Operand &src, const Register &dest) {
         switch (src.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.leaq_mr(src.disp(), src.base(), dest.code());
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.leaq_mr(src.disp(), src.base(), src.index(), src.scale(), dest.code());
             break;
           default:
@@ -618,7 +618,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.cmpq_rr(rhs.code(), lhs.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpq_rm(rhs.code(), lhs.disp(), lhs.base());
             break;
           default:
@@ -630,7 +630,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.cmpq_ir(rhs.value, lhs.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpq_im(rhs.value, lhs.disp(), lhs.base());
             break;
           default:
@@ -642,7 +642,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.cmpq_rr(rhs.reg(), lhs.code());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpq_mr(rhs.disp(), rhs.base(), lhs.code());
             break;
           default:
@@ -667,7 +667,7 @@ class Assembler : public AssemblerX86Shared
           case Operand::REG:
             masm.testq_i32r(rhs.value, lhs.reg());
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.testq_i32m(rhs.value, lhs.disp(), lhs.base());
             break;
           default:
diff --git a/js/src/jit/x64/CodeGenerator-x64.cpp b/js/src/jit/x64/CodeGenerator-x64.cpp
index 5bc9dc89a3c..e7053241dda 100644
--- a/js/src/jit/x64/CodeGenerator-x64.cpp
+++ b/js/src/jit/x64/CodeGenerator-x64.cpp
@@ -241,7 +241,7 @@ CodeGeneratorX64::visitLoadElementT(LLoadElementT *load)
 
     if (load->mir()->loadDoubles()) {
         FloatRegister fpreg = ToFloatRegister(load->output());
-        if (source.kind() == Operand::REG_DISP)
+        if (source.kind() == Operand::MEM_REG_DISP)
             masm.loadDouble(source.toAddress(), fpreg);
         else
             masm.loadDouble(source.toBaseIndex(), fpreg);
diff --git a/js/src/jit/x64/MacroAssembler-x64.h b/js/src/jit/x64/MacroAssembler-x64.h
index 1cf14075b08..677ca6689fb 100644
--- a/js/src/jit/x64/MacroAssembler-x64.h
+++ b/js/src/jit/x64/MacroAssembler-x64.h
@@ -106,10 +106,10 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
     // On x86_64, the upper 32 bits do not necessarily only contain the type.
     Operand ToUpper32(Operand base) {
         switch (base.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             return Operand(Register::FromCode(base.base()), base.disp() + 4);
 
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             return Operand(Register::FromCode(base.base()), Register::FromCode(base.index()),
                            base.scale(), base.disp() + 4);
 
diff --git a/js/src/jit/x86/Assembler-x86.h b/js/src/jit/x86/Assembler-x86.h
index 71123c4eb67..ed758fde03a 100644
--- a/js/src/jit/x86/Assembler-x86.h
+++ b/js/src/jit/x86/Assembler-x86.h
@@ -113,10 +113,10 @@ class Operand
   public:
     enum Kind {
         REG,
-        REG_DISP,
+        MEM_REG_DISP,
         FPREG,
-        SCALE,
-        ADDRESS
+        MEM_SCALE,
+        MEM_ADDRESS
     };
 
     Kind kind_ : 4;
@@ -135,45 +135,45 @@ class Operand
         base_(reg.code())
     { }
     explicit Operand(const Address &address)
-      : kind_(REG_DISP),
+      : kind_(MEM_REG_DISP),
         base_(address.base.code()),
         disp_(address.offset)
     { }
     explicit Operand(const BaseIndex &address)
-      : kind_(SCALE),
+      : kind_(MEM_SCALE),
         index_(address.index.code()),
         scale_(address.scale),
         base_(address.base.code()),
         disp_(address.offset)
     { }
     Operand(Register base, Register index, Scale scale, int32_t disp = 0)
-      : kind_(SCALE),
+      : kind_(MEM_SCALE),
         index_(index.code()),
         scale_(scale),
         base_(base.code()),
         disp_(disp)
     { }
     Operand(Register reg, int32_t disp)
-      : kind_(REG_DISP),
+      : kind_(MEM_REG_DISP),
         base_(reg.code()),
         disp_(disp)
     { }
     explicit Operand(const AbsoluteAddress &address)
-      : kind_(ADDRESS),
+      : kind_(MEM_ADDRESS),
         base_(reinterpret_cast<int32_t>(address.addr))
     { }
     explicit Operand(const void *address)
-      : kind_(ADDRESS),
+      : kind_(MEM_ADDRESS),
         base_(reinterpret_cast<int32_t>(address))
     { }
 
     Address toAddress() {
-        JS_ASSERT(kind() == REG_DISP);
+        JS_ASSERT(kind() == MEM_REG_DISP);
         return Address(Register::FromCode(base()), disp());
     }
 
     BaseIndex toBaseIndex() {
-        JS_ASSERT(kind() == SCALE);
+        JS_ASSERT(kind() == MEM_SCALE);
         return BaseIndex(Register::FromCode(base()), Register::FromCode(index()), scale(), disp());
     }
 
@@ -185,15 +185,15 @@ class Operand
         return (Registers::Code)base_;
     }
     Registers::Code base() const {
-        JS_ASSERT(kind() == REG_DISP || kind() == SCALE);
+        JS_ASSERT(kind() == MEM_REG_DISP || kind() == MEM_SCALE);
         return (Registers::Code)base_;
     }
     Registers::Code index() const {
-        JS_ASSERT(kind() == SCALE);
+        JS_ASSERT(kind() == MEM_SCALE);
         return (Registers::Code)index_;
     }
     Scale scale() const {
-        JS_ASSERT(kind() == SCALE);
+        JS_ASSERT(kind() == MEM_SCALE);
         return scale_;
     }
     FloatRegisters::Code fpu() const {
@@ -201,11 +201,11 @@ class Operand
         return (FloatRegisters::Code)base_;
     }
     int32_t disp() const {
-        JS_ASSERT(kind() == REG_DISP || kind() == SCALE);
+        JS_ASSERT(kind() == MEM_REG_DISP || kind() == MEM_SCALE);
         return disp_;
     }
     void *address() const {
-        JS_ASSERT(kind() == ADDRESS);
+        JS_ASSERT(kind() == MEM_ADDRESS);
         return reinterpret_cast<void *>(base_);
     }
 };
@@ -309,11 +309,11 @@ class Assembler : public AssemblerX86Shared
             masm.movl_i32r(ptr.value, dest.reg());
             writeDataRelocation(ptr);
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.movl_i32m(ptr.value, dest.disp(), dest.base());
             writeDataRelocation(ptr);
             break;
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             masm.movl_i32m(ptr.value, dest.disp(), dest.base(), dest.index(), dest.scale());
             writeDataRelocation(ptr);
             break;
@@ -381,11 +381,11 @@ class Assembler : public AssemblerX86Shared
             masm.cmpl_ir_force32(imm.value, op.reg());
             writeDataRelocation(imm);
             break;
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             masm.cmpl_im_force32(imm.value, op.disp(), op.base());
             writeDataRelocation(imm);
             break;
-          case Operand::ADDRESS:
+          case Operand::MEM_ADDRESS:
             masm.cmpl_im(imm.value, op.address());
             writeDataRelocation(imm);
             break;
diff --git a/js/src/jit/x86/CodeGenerator-x86.cpp b/js/src/jit/x86/CodeGenerator-x86.cpp
index 06d250f5536..0e5be3c5b56 100644
--- a/js/src/jit/x86/CodeGenerator-x86.cpp
+++ b/js/src/jit/x86/CodeGenerator-x86.cpp
@@ -210,7 +210,7 @@ CodeGeneratorX86::visitLoadElementT(LLoadElementT *load)
     if (load->mir()->type() == MIRType_Double) {
         FloatRegister fpreg = ToFloatRegister(load->output());
         if (load->mir()->loadDoubles()) {
-            if (source.kind() == Operand::REG_DISP)
+            if (source.kind() == Operand::MEM_REG_DISP)
                 masm.loadDouble(source.toAddress(), fpreg);
             else
                 masm.loadDouble(source.toBaseIndex(), fpreg);
diff --git a/js/src/jit/x86/MacroAssembler-x86.h b/js/src/jit/x86/MacroAssembler-x86.h
index c707f9b743b..4b9e251df08 100644
--- a/js/src/jit/x86/MacroAssembler-x86.h
+++ b/js/src/jit/x86/MacroAssembler-x86.h
@@ -98,10 +98,10 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
     }
     Operand ToType(Operand base) {
         switch (base.kind()) {
-          case Operand::REG_DISP:
+          case Operand::MEM_REG_DISP:
             return Operand(Register::FromCode(base.base()), base.disp() + sizeof(void *));
 
-          case Operand::SCALE:
+          case Operand::MEM_SCALE:
             return Operand(Register::FromCode(base.base()), Register::FromCode(base.index()),
                            base.scale(), base.disp() + sizeof(void *));
 
@@ -174,7 +174,7 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
         // Ensure that loading the payload does not erase the pointer to the
         // Value in memory or the index.
         Register baseReg = Register::FromCode(src.base());
-        Register indexReg = (src.kind() == Operand::SCALE) ? Register::FromCode(src.index()) : InvalidReg;
+        Register indexReg = (src.kind() == Operand::MEM_SCALE) ? Register::FromCode(src.index()) : InvalidReg;
 
         if (baseReg == val.payloadReg() || indexReg == val.payloadReg()) {
             JS_ASSERT(baseReg != val.typeReg());