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Bug 504213: nanojit: rename LIR_alloc, LIR_addp, LIR_param to match tamarin-redux. r=graydon.

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This commit is contained in:
Nicholas Nethercote 2009-07-15 10:00:43 +10:00
parent 6eb09ec1ad
commit acc2840ef2
9 changed files with 59 additions and 59 deletions
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4
js/src/lirasm/lirasm.cpp
View File

@ -767,13 +767,13 @@ assemble(istream &in,
labels, line);
break;
case LIR_param:
case LIR_iparam:
need(toks, 2, line);
ins = lir->insParam(imm(toks[0]),
imm(toks[1]));
break;
case LIR_alloc:
case LIR_ialloc:
need(toks, 1, line);
ins = lir->insAlloc(imm(toks[0]));
break;

18
js/src/nanojit/Assembler.cpp
View File

@ -255,7 +255,7 @@ namespace nanojit
* they can just be recalculated w/out any inputs.
*/
bool Assembler::canRemat(LIns *i) {
return i->isconst() || i->isconstq() || i->isop(LIR_alloc);
return i->isconst() || i->isconstq() || i->isop(LIR_ialloc);
}
void Assembler::internalReset()
@ -403,7 +403,7 @@ namespace nanojit
Reservation *r = getresv(ins);
NanoAssert(r != 0);
if (r->arIndex) {
if (ins->isop(LIR_alloc)) {
if (ins->isop(LIR_ialloc)) {
int j=i+1;
for (int n = i + (ins->size()>>2); j < n; j++) {
NanoAssert(ar.entry[j]==ins);
@ -495,7 +495,7 @@ namespace nanojit
Register Assembler::getBaseReg(LIns *i, int &d, RegisterMask allow)
{
if (i->isop(LIR_alloc)) {
if (i->isop(LIR_ialloc)) {
d += findMemFor(i);
return FP;
} else {
@ -505,7 +505,7 @@ namespace nanojit
Register Assembler::findRegFor(LIns* i, RegisterMask allow)
{
if (i->isop(LIR_alloc)) {
if (i->isop(LIR_ialloc)) {
// never allocate a reg for this w/out stack space too
findMemFor(i);
}
@ -597,7 +597,7 @@ namespace nanojit
{
int d = disp(resv);
Register rr = resv->reg;
bool quad = i->opcode() == LIR_param || i->isQuad();
bool quad = i->opcode() == LIR_iparam || i->isQuad();
verbose_only( if (d && (_logc->lcbits & LC_RegAlloc)) {
outputForEOL(" <= spill %s",
_thisfrag->lirbuf->names->formatRef(i)); } )
@ -1176,7 +1176,7 @@ namespace nanojit
// allocate some stack space. the value of this instruction
// is the address of the stack space.
case LIR_alloc: {
case LIR_ialloc: {
countlir_alloc();
Reservation *resv = getresv(ins);
NanoAssert(resv->arIndex != 0);
@ -1211,7 +1211,7 @@ namespace nanojit
break;
}
#endif
case LIR_param:
case LIR_iparam:
{
countlir_param();
asm_param(ins);
@ -1278,7 +1278,7 @@ namespace nanojit
#endif
case LIR_add:
case LIR_addp:
case LIR_iaddp:
case LIR_sub:
case LIR_mul:
case LIR_and:
@ -1663,7 +1663,7 @@ namespace nanojit
uint32_t Assembler::arReserve(LIns* l)
{
//verbose_only(printActivationState());
int32_t size = l->isop(LIR_alloc) ? (l->size()>>2) : l->isQuad() ? 2 : sizeof(intptr_t)>>2;
int32_t size = l->isop(LIR_ialloc) ? (l->size()>>2) : l->isQuad() ? 2 : sizeof(intptr_t)>>2;
AR &ar = _activation;
const int32_t tos = ar.tos;
int32_t start = ar.lowwatermark;

12
js/src/nanojit/LIR.cpp
View File

@ -294,7 +294,7 @@ namespace nanojit
size = (size+3)>>2; // # of required 32bit words
LInsI* insI = (LInsI*)_buf->makeRoom(sizeof(LInsI));
LIns* ins = insI->getLIns();
ins->initLInsI(LIR_alloc, size);
ins->initLInsI(LIR_ialloc, size);
return ins;
}
@ -779,7 +779,7 @@ namespace nanojit
LIns* t;
switch (v) {
case LIR_add:
case LIR_addp:
case LIR_iaddp:
case LIR_mul:
case LIR_fadd:
case LIR_fmul:
@ -845,7 +845,7 @@ namespace nanojit
if (c == 0) {
switch (v) {
case LIR_add:
case LIR_addp:
case LIR_iaddp:
case LIR_or:
case LIR_xor:
case LIR_sub:
@ -1691,7 +1691,7 @@ namespace nanojit
break;
}
case LIR_alloc: {
case LIR_ialloc: {
sprintf(s, "%s = %s %d", formatRef(i), lirNames[op], i->size());
break;
}
@ -1722,7 +1722,7 @@ namespace nanojit
break;
}
case LIR_param: {
case LIR_iparam: {
uint32_t arg = i->paramArg();
if (!i->paramKind()) {
if (arg < sizeof(Assembler::argRegs)/sizeof(Assembler::argRegs[0])) {
@ -1781,7 +1781,7 @@ namespace nanojit
break;
case LIR_add:
case LIR_addp:
case LIR_iaddp:
case LIR_sub:
case LIR_mul:
case LIR_div:

12
js/src/nanojit/LIR.h
View File

@ -396,7 +396,7 @@ namespace nanojit
LIns* getLIns() { return (LIns*)&ins; };
};
// Used for LIR_param.
// Used for LIR_iparam.
class LInsP
{
private:
@ -411,7 +411,7 @@ namespace nanojit
LIns* getLIns() { return (LIns*)&ins; };
};
// Used for LIR_int and LIR_alloc.
// Used for LIR_int and LIR_ialloc.
class LInsI
{
private:
@ -556,7 +556,7 @@ namespace nanojit
}
void initLInsP(int32_t arg, int32_t kind) {
lastWord.clear();
lastWord.opcode = LIR_param;
lastWord.opcode = LIR_iparam;
NanoAssert(isU8(arg) && isU8(kind));
toLInsP()->arg = arg;
toLInsP()->kind = kind;
@ -591,8 +591,8 @@ namespace nanojit
}
inline LOpcode opcode() const { return lastWord.opcode; }
inline uint8_t paramArg() const { NanoAssert(isop(LIR_param)); return toLInsP()->arg; }
inline uint8_t paramKind() const { NanoAssert(isop(LIR_param)); return toLInsP()->kind; }
inline uint8_t paramArg() const { NanoAssert(isop(LIR_iparam)); return toLInsP()->arg; }
inline uint8_t paramKind() const { NanoAssert(isop(LIR_iparam)); return toLInsP()->kind; }
inline int32_t imm32() const { NanoAssert(isconst()); return toLInsI()->imm32; }
inline int32_t imm64_0() const { NanoAssert(isconstq()); return toLInsI64()->imm64_0; }
inline int32_t imm64_1() const { NanoAssert(isconstq()); return toLInsI64()->imm64_1; }
@ -602,7 +602,7 @@ namespace nanojit
void* payload() const;
inline Page* page() { return (Page*) alignTo(this,NJ_PAGE_SIZE); }
inline int32_t size() const {
NanoAssert(isop(LIR_alloc));
NanoAssert(isop(LIR_ialloc));
return toLInsI()->imm32 << 2;
}

6
js/src/nanojit/LIRopcode.tbl
View File

@ -77,11 +77,11 @@ OPDEF(unused5, 5,-1, None)
OPDEF(unused6, 6,-1, None)
/* non-pure operations */
OPDEF(addp, 7, 2, Op2) // integer addition for temporary pointer calculations
OPDEF(param, 8, 0, P) // load a parameter
OPDEF(iaddp, 7, 2, Op2) // 32-bit integer addition for temporary pointer calculations
OPDEF(iparam, 8, 0, P) // load a parameter (32-bit register or stack location)
OPDEF(unused9, 9,-1, None)
OPDEF(ld, 10, 1, Ld) // 32-bit load
OPDEF(alloc, 11, 0, I) // alloca some stack space
OPDEF(ialloc, 11, 0, I) // alloca some stack space
OPDEF(sti, 12, 2, Sti) // 32-bit store
OPDEF(ret, 13, 1, Op1) // return a word-sized value
OPDEF(live, 14, 1, Op1) // extend live range of reference

16
js/src/nanojit/NativeARM.cpp
View File

@ -373,7 +373,7 @@ Assembler::asm_arg(ArgSize sz, LInsp arg, Register& r, int& stkd)
if (argRes->reg == UnknownReg) {
// load it into the arg reg
int d = findMemFor(arg);
if (arg->isop(LIR_alloc)) {
if (arg->isop(LIR_ialloc)) {
asm_add_imm(r, FP, d);
} else {
LDR(r, FP, d);
@ -393,7 +393,7 @@ Assembler::asm_arg(ArgSize sz, LInsp arg, Register& r, int& stkd)
} else {
int d = findMemFor(arg);
STR_preindex(IP, SP, -4);
if (arg->isop(LIR_alloc)) {
if (arg->isop(LIR_ialloc)) {
asm_add_imm(IP, FP, d);
} else {
LDR(IP, FP, d);
@ -616,7 +616,7 @@ Assembler::hint(LIns* i, RegisterMask allow /* = ~0 */)
prefer = rmask(R0);
else if (op == LIR_callh)
prefer = rmask(R1);
else if (op == LIR_param)
else if (op == LIR_iparam)
prefer = rmask(imm2register(i->paramArg()));
if (_allocator.free & allow & prefer)
@ -646,7 +646,7 @@ Assembler::asm_store32(LIns *value, int dr, LIns *base)
{
Reservation *rA, *rB;
Register ra, rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
ra = findRegFor(value, GpRegs);
@ -661,7 +661,7 @@ Assembler::asm_store32(LIns *value, int dr, LIns *base)
void
Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
{
if (i->isop(LIR_alloc)) {
if (i->isop(LIR_ialloc)) {
asm_add_imm(r, FP, disp(resv));
} else if (IsFpReg(r)) {
NanoAssert(AvmCore::config.vfp);
@ -1739,7 +1739,7 @@ Assembler::asm_arith(LInsp ins)
rb = findRegFor(rhs, allow);
}
allow &= ~rmask(rb);
} else if ((op == LIR_add||op == LIR_addp) && lhs->isop(LIR_alloc) && rhs->isconst()) {
} else if ((op == LIR_add||op == LIR_iaddp) && lhs->isop(LIR_ialloc) && rhs->isconst()) {
// add alloc+const, rr wants the address of the allocated space plus a constant
Register rr = prepResultReg(ins, allow);
int d = findMemFor(lhs) + rhs->imm32();
@ -1759,7 +1759,7 @@ Assembler::asm_arith(LInsp ins)
if (lhs == rhs)
rb = ra;
if (op == LIR_add || op == LIR_addp)
if (op == LIR_add || op == LIR_iaddp)
ADDs(rr, ra, rb, 1);
else if (op == LIR_sub)
SUB(rr, ra, rb);
@ -1784,7 +1784,7 @@ Assembler::asm_arith(LInsp ins)
NanoAssertMsg(0, "Unsupported");
} else {
int c = rhs->imm32();
if (op == LIR_add || op == LIR_addp)
if (op == LIR_add || op == LIR_iaddp)
ADDi(rr, ra, c);
else if (op == LIR_sub)
SUBi(rr, ra, c);

6
js/src/nanojit/NativePPC.cpp
View File

@ -580,7 +580,7 @@ namespace nanojit
void Assembler::asm_restore(LIns *i, Reservation *resv, Register r) {
int d;
if (i->isop(LIR_alloc)) {
if (i->isop(LIR_ialloc)) {
d = disp(resv);
ADDI(r, FP, d);
}
@ -734,7 +734,7 @@ namespace nanojit
if (rA->reg == UnknownReg) {
// load it into the arg reg
int d = findMemFor(p);
if (p->isop(LIR_alloc)) {
if (p->isop(LIR_ialloc)) {
NanoAssert(isS16(d));
ADDI(r, FP, d);
} else if (p->isQuad()) {
@ -1144,7 +1144,7 @@ namespace nanojit
prefer = rmask(R3);
else if (op == LIR_fcall)
prefer = rmask(F1);
else if (op == LIR_param) {
else if (op == LIR_iparam) {
if (i->imm8() < 8) {
prefer = rmask(argRegs[i->imm8()]);
}

16
js/src/nanojit/NativeSparc.cpp
View File

@ -282,7 +282,7 @@ namespace nanojit
void Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
{
underrunProtect(24);
if (i->isop(LIR_alloc)) {
if (i->isop(LIR_ialloc)) {
ADD(FP, L2, r);
SET32(disp(resv), L2);
verbose_only(if (_logc->lcbits & LC_RegAlloc) {
@ -323,7 +323,7 @@ namespace nanojit
// make sure what is in a register
Reservation *rA, *rB;
Register ra, rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
ra = findRegFor(value, GpRegs);
@ -364,7 +364,7 @@ namespace nanojit
int dr = disp(resv);
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
db += findMemFor(base);
} else {
@ -414,7 +414,7 @@ namespace nanojit
int da = findMemFor(value);
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
} else {
@ -425,7 +425,7 @@ namespace nanojit
}
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
} else {
@ -649,7 +649,7 @@ namespace nanojit
}
allow &= ~rmask(rb);
}
else if ((op == LIR_add||op == LIR_addp) && lhs->isop(LIR_alloc) && rhs->isconst()) {
else if ((op == LIR_add||op == LIR_iaddp) && lhs->isop(LIR_ialloc) && rhs->isconst()) {
// add alloc+const, use lea
Register rr = prepResultReg(ins, allow);
int d = findMemFor(lhs) + rhs->imm32();
@ -670,7 +670,7 @@ namespace nanojit
if (lhs == rhs)
rb = ra;
if (op == LIR_add || op == LIR_addp)
if (op == LIR_add || op == LIR_iaddp)
ADDCC(rr, rb, rr);
else if (op == LIR_sub)
SUBCC(rr, rb, rr);
@ -694,7 +694,7 @@ namespace nanojit
else
{
int c = rhs->imm32();
if (op == LIR_add || op == LIR_addp) {
if (op == LIR_add || op == LIR_iaddp) {
ADDCC(rr, L2, rr);
} else if (op == LIR_sub) {
SUBCC(rr, L2, rr);

28
js/src/nanojit/Nativei386.cpp
View File

@ -342,7 +342,7 @@ namespace nanojit
else if (op == LIR_fcall) {
prefer &= rmask(FST0);
}
else if (op == LIR_param) {
else if (op == LIR_iparam) {
uint32_t max_regs = max_abi_regs[_thisfrag->lirbuf->abi];
if (i->paramArg() < max_regs)
prefer &= rmask(Register(i->paramArg()));
@ -414,7 +414,7 @@ namespace nanojit
void Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
{
if (i->isop(LIR_alloc)) {
if (i->isop(LIR_ialloc)) {
verbose_only( if (_logc->lcbits & LC_RegAlloc) {
outputForEOL(" <= remat %s size %d",
_thisfrag->lirbuf->names->formatRef(i), i->size()); } )
@ -448,7 +448,7 @@ namespace nanojit
// make sure what is in a register
Reservation *rA, *rB;
Register ra, rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
ra = findRegFor(value, GpRegs);
@ -509,7 +509,7 @@ namespace nanojit
{
int dr = disp(resv);
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
db += findMemFor(base);
} else {
@ -539,7 +539,7 @@ namespace nanojit
// if a constant 64-bit value just store it now rather than
// generating a pointless store/load/store sequence
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
} else {
@ -564,7 +564,7 @@ namespace nanojit
if (config.sse2) {
Register rv = findRegFor(value, XmmRegs);
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
} else {
@ -576,7 +576,7 @@ namespace nanojit
int da = findMemFor(value);
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
} else {
@ -587,7 +587,7 @@ namespace nanojit
}
Register rb;
if (base->isop(LIR_alloc)) {
if (base->isop(LIR_ialloc)) {
rb = FP;
dr += findMemFor(base);
} else {
@ -843,8 +843,8 @@ namespace nanojit
}
break;
case LIR_add:
case LIR_addp:
if (lhs->isop(LIR_alloc) && rhs->isconst()) {
case LIR_iaddp:
if (lhs->isop(LIR_ialloc) && rhs->isconst()) {
// add alloc+const, use lea
Register rr = prepResultReg(ins, allow);
int d = findMemFor(lhs) + rhs->imm32();
@ -879,7 +879,7 @@ namespace nanojit
switch (op) {
case LIR_add:
case LIR_addp:
case LIR_iaddp:
ADD(rr, rb);
break;
case LIR_sub:
@ -919,7 +919,7 @@ namespace nanojit
{
int c = rhs->imm32();
switch (op) {
case LIR_addp:
case LIR_iaddp:
// this doesn't set cc's, only use it when cc's not required.
LEA(rr, c, ra);
ra = rr; // suppress mov
@ -1302,7 +1302,7 @@ namespace nanojit
if (rA->reg == UnknownReg) {
// load it into the arg reg
int d = findMemFor(p);
if (p->isop(LIR_alloc)) {
if (p->isop(LIR_ialloc)) {
LEA(r, d, FP);
} else {
LD(r, d, FP);
@ -1339,7 +1339,7 @@ namespace nanojit
// small const we push directly
PUSHi(p->imm32());
}
else if (rA == 0 || p->isop(LIR_alloc))
else if (rA == 0 || p->isop(LIR_ialloc))
{
Register ra = findRegFor(p, GpRegs);
PUSHr(ra);