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Bug 523952 - typos and cleanup from tamarin, r=gal.

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--HG--
extra : rebase_source : da1dcdcc6c1f21f73b2223dcdb611c17a9018190
This commit is contained in:
Graydon Hoare 2009-10-22 14:29:37 -07:00
parent 7d3329fbfb
commit 951aacba56
6 changed files with 29 additions and 28 deletions
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2
js/src/nanojit/CodeAlloc.cpp
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@ -244,7 +244,7 @@ namespace nanojit
#if defined NANOJIT_ARM && defined UNDER_CE
// Use a single flush for the whole CodeList, when we have no
// finer-granularity flush support, as on WinCE.
void CodeAlloc::flushICache(CodeList* &blocks) {
void CodeAlloc::flushICache(CodeList*) {
FlushInstructionCache(GetCurrentProcess(), NULL, NULL);
}
#else

2
js/src/nanojit/LIR.cpp
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@ -927,7 +927,7 @@ namespace nanojit
#ifdef NJ_SOFTFLOAT
if (!ARM_VFP && (op == LIR_fcall || op == LIR_qcall))
op = LIR_callh;
op = LIR_callh;
#endif
NanoAssert(argc <= (int)MAXARGS);

27
js/src/nanojit/NativeARM.cpp
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@ -45,21 +45,7 @@
extern "C" bool blx_lr_broken();
#endif
#if defined(AVMPLUS_LINUX)
#include <signal.h>
#include <setjmp.h>
#include <asm/unistd.h>
extern "C" void __clear_cache(void *BEG, void *END);
#endif
// assume EABI, except under CE
#ifdef UNDER_CE
#undef NJ_ARM_EABI
#else
#define NJ_ARM_EABI
#endif
#ifdef FEATURE_NANOJIT
#if defined(FEATURE_NANOJIT) && defined(NANOJIT_ARM)
namespace nanojit
{
@ -762,8 +748,8 @@ Assembler::asm_regarg(ArgSize sz, LInsp p, Register r)
void
Assembler::asm_stkarg(LInsp arg, int stkd)
{
Reservation* argRes = getresv(arg);
bool isQuad = arg->isQuad();
Reservation* argRes = getresv(arg);
bool isQuad = arg->isQuad();
if (argRes && (argRes->reg != UnknownReg)) {
// The argument resides somewhere in registers, so we simply need to
@ -817,9 +803,9 @@ Assembler::asm_stkarg(LInsp arg, int stkd)
void
Assembler::asm_call(LInsp ins)
{
const CallInfo* call = ins->callInfo();
ArgSize sizes[MAXARGS];
uint32_t argc = call->get_sizes(sizes);
const CallInfo* call = ins->callInfo();
ArgSize sizes[MAXARGS];
uint32_t argc = call->get_sizes(sizes);
bool indirect = call->isIndirect();
// If we aren't using VFP, assert that the LIR operation is an integer
@ -1127,6 +1113,7 @@ Assembler::asm_load64(LInsp ins)
// Either VFP is not available or the result needs to go into memory;
// in either case, VFP instructions are not required. Note that the
// result will never be loaded into registers if VFP is not available.
NanoAssert(resv->reg == UnknownReg);
NanoAssert(d != 0);
// Check that the offset is 8-byte (64-bit) aligned.

22
js/src/nanojit/NativeARM.h
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@ -56,6 +56,22 @@
namespace nanojit
{
#if defined VMCFG_DOUBLE_MSW_FIRST || defined _MSC_VER
# undef NJ_ARM_EABI
#else
# define NJ_ARM_EABI 1
#endif
// default to ARMv5
#if !defined(ARM_ARCH)
# define ARM_ARCH 5
#endif
// default to no-thumb2
#if !defined(ARM_THUMB2)
# define ARM_THUMB2 0
#endif
// only d0-d6 are actually used; we'll use d7 as s14-s15 for i2f/u2f/etc.
#define NJ_VFP_MAX_REGISTERS 8
#define NJ_MAX_REGISTERS (11 + NJ_VFP_MAX_REGISTERS)
@ -108,9 +124,9 @@ typedef enum {
FirstFloatReg = D0,
LastFloatReg = D6,
FirstReg = 0,
LastReg = 22, // This excludes D7 from the register allocator.
UnknownReg = 31,
FirstReg = R0,
LastReg = D6,
UnknownReg = 32,
// special value referring to S14
FpSingleScratch = 24

3
js/src/nanojit/NativePPC.h
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@ -243,7 +243,6 @@ namespace nanojit
static const RegisterMask GpRegs = 0xffffffff;
static const RegisterMask FpRegs = 0xffffffff00000000LL;
static const bool CalleeRegsNeedExplicitSaving = true;
// R31 is a saved reg too, but we use it as our Frame ptr FP
#ifdef NANOJIT_64BIT
// R13 reserved for thread-specific storage on ppc64-darwin
@ -299,7 +298,7 @@ namespace nanojit
typedef uint32_t NIns;
// Bytes of icache to flush after Assembler::patch
const size_t LARGEST_BRANCH_PATCH = 4 * sizeof(Nins);
const size_t LARGEST_BRANCH_PATCH = 4 * sizeof(NIns);
inline Register nextreg(Register r) {
return Register(r+1);

1
js/src/nanojit/NativeX64.h
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@ -309,7 +309,6 @@ namespace nanojit
static const RegisterMask GpRegs = 0xffff;
static const RegisterMask FpRegs = 0xffff0000;
static const bool CalleeRegsNeedExplicitSaving = true;
#ifdef _MSC_VER
static const RegisterMask SavedRegs = 1<<RBX | 1<<RSI | 1<<RDI | 1<<R12 | 1<<R13 | 1<<R14 | 1<<R15;
static const int NumSavedRegs = 7; // rbx, rsi, rdi, r12-15