Bug 512366 - insert some missing assembler bits, r=dvander.

js/src/nanojit/Assembler.h

@@ -270,6 +270,7 @@ namespace nanojit
             void        asm_spill(Register rr, int d, bool pop, bool quad);
             void        asm_load64(LInsp i);
             void        asm_pusharg(LInsp p);
+            void        asm_ret(LInsp p);
             void        asm_quad(LInsp i);
             void        asm_loop(LInsp i, NInsList& loopJumps);
             void        asm_fcond(LInsp i);
@@ -287,6 +288,7 @@ namespace nanojit
             void        asm_fop(LInsp ins);
             void        asm_i2f(LInsp ins);
             void        asm_u2f(LInsp ins);
+            void        asm_promote(LIns *ins);
             Register    asm_prep_fcall(Reservation *rR, LInsp ins);
             void        asm_nongp_copy(Register r, Register s);
             void        asm_call(LInsp);

js/src/nanojit/NativeARM.cpp

@@ -2387,6 +2387,40 @@ Assembler::asm_int(LInsp ins)
     asm_ld_imm(rr, ins->imm32());
 }
 
+void
+Assembler::asm_ret(LIns *ins)
+{
+    if (_nIns != _epilogue) {
+        B(_epilogue);
+    }
+    assignSavedRegs();
+    LIns *value = ins->oprnd1();
+    if (ins->isop(LIR_ret)) {
+        findSpecificRegFor(value, R0);
+    }
+    else {
+        NanoAssert(ins->isop(LIR_fret));
+#ifdef NJ_ARM_VFP
+        Register reg = findRegFor(value, FpRegs);
+        FMRRD(R0, R1, reg);
+#else
+        NanoAssert(value->isop(LIR_qjoin));
+        findSpecificRegFor(value->oprnd1(), R0); // lo
+        findSpecificRegFor(value->oprnd2(), R1); // hi
+#endif
+    }
+}
+
+void
+Assembler::asm_promote(LIns *ins)
+{
+    /* The LIR opcodes that result in a call to asm_promote are only generated
+     * if NANOJIT_64BIT is #define'd, which it never is for ARM.
+     */
+    (void)ins;
+    NanoAssert(0);
+}
+
 }
 
 #endif /* FEATURE_NANOJIT */

js/src/nanojit/NativeSparc.cpp

@@ -68,6 +68,7 @@ namespace nanojit
     static const int kcalleeAreaSize = 80; // The max size.
     static const int NJ_PAGE_SIZE_SPARC = 8192; // Use sparc page size here.
 
+#define TODO(x) do{ verbose_only(outputf(#x);) NanoAssertMsgf(false, "%s", #x); } while(0)
 #define BIT_ROUND_UP(v,q)      ( (((uintptr_t)v)+(q)-1) & ~((q)-1) )
 
     void Assembler::nInit(AvmCore* core)
@@ -1071,7 +1072,6 @@ namespace nanojit
         }
     }
 
-/*
     void Assembler::asm_ret(LInsp ins)
     {
         if (_nIns != _epilogue) {
@@ -1085,7 +1085,11 @@ namespace nanojit
             findSpecificRegFor(val, F0);
         }
     }
-*/
+
+    void Assembler::asm_promote(LIns *) {
+        // i2q or u2q
+        TODO(asm_promote);
+    }
 
 #endif /* FEATURE_NANOJIT */
 }

js/src/nanojit/Nativei386.cpp

@@ -63,6 +63,8 @@ namespace nanojit
         };
     #endif
 
+    #define TODO(x) do{ verbose_only(outputf(#x);) NanoAssertMsgf(false, "%s", #x); } while(0)
+
     const Register Assembler::argRegs[] = { ECX, EDX };
     const Register Assembler::retRegs[] = { EAX, EDX };
     const Register Assembler::savedRegs[] = { EBX, ESI, EDI };
@@ -1697,5 +1699,27 @@ namespace nanojit
         }
     }
 
+    void Assembler::asm_ret(LInsp ins)
+    {
+        if (_nIns != _epilogue) {
+            JMP(_epilogue);
+        }
+        assignSavedRegs();
+        LIns *val = ins->oprnd1();
+        if (ins->isop(LIR_ret)) {
+            findSpecificRegFor(val, retRegs[0]);
+        } else {
+            findSpecificRegFor(val, FST0);
+            fpu_pop();
+        }
+    }
+
+    void Assembler::asm_promote(LIns *) {
+        // i2q or u2q
+        TODO(asm_promote);
+    }
+
+
+
     #endif /* FEATURE_NANOJIT */
 }