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[arm] b=481761; fix up asm_cmov; assert on non-qcmov; r=graydon
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@ -1478,7 +1478,7 @@ Assembler::asm_ld(LInsp ins)
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void
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Assembler::asm_cmov(LInsp ins)
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{
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LOpcode op = ins->opcode();
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NanoAssert(ins->opcode() == LIR_cmov);
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LIns* condval = ins->oprnd1();
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NanoAssert(condval->isCmp());
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@ -1488,14 +1488,13 @@ Assembler::asm_cmov(LInsp ins)
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LIns* iftrue = values->oprnd1();
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LIns* iffalse = values->oprnd2();
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NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad()));
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NanoAssert(!iftrue->isQuad() && !iffalse->isQuad());
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const Register rr = prepResultReg(ins, GpRegs);
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// this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
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// (This is true on Intel, is it true on all architectures?)
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const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr));
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if (op == LIR_cmov) {
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switch (condval->opcode()) {
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// note that these are all opposites...
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case LIR_eq: MOVNE(rr, iffalsereg); break;
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@ -1511,9 +1510,6 @@ Assembler::asm_cmov(LInsp ins)
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case LIR_uge: MOVB(rr, iffalsereg); break;
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default: debug_only( NanoAssert(0) ); break;
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}
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} else if (op == LIR_qcmov) {
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NanoAssert(0);
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}
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/*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
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asm_cmp(condval);
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}
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