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[arm] b=481761; fix up asm_cmov; assert on non-qcmov; r=graydon

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This commit is contained in:
Vladimir Vukicevic 2009-03-20 15:53:14 -07:00
parent d0fa8fe9c9
commit 7d6eca6372
1 changed files with 16 additions and 20 deletions
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36
js/src/nanojit/NativeARM.cpp
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@ -1478,7 +1478,7 @@ Assembler::asm_ld(LInsp ins)
void void
Assembler::asm_cmov(LInsp ins) Assembler::asm_cmov(LInsp ins)
{ {
LOpcode op = ins->opcode(); NanoAssert(ins->opcode() == LIR_cmov);
LIns* condval = ins->oprnd1(); LIns* condval = ins->oprnd1();
NanoAssert(condval->isCmp()); NanoAssert(condval->isCmp());
@ -1488,31 +1488,27 @@ Assembler::asm_cmov(LInsp ins)
LIns* iftrue = values->oprnd1(); LIns* iftrue = values->oprnd1();
LIns* iffalse = values->oprnd2(); LIns* iffalse = values->oprnd2();
NanoAssert(op == LIR_qcmov || (!iftrue->isQuad() && !iffalse->isQuad())); NanoAssert(!iftrue->isQuad() && !iffalse->isQuad());
const Register rr = prepResultReg(ins, GpRegs); const Register rr = prepResultReg(ins, GpRegs);
// this code assumes that neither LD nor MR nor MRcc set any of the condition flags. // this code assumes that neither LD nor MR nor MRcc set any of the condition flags.
// (This is true on Intel, is it true on all architectures?) // (This is true on Intel, is it true on all architectures?)
const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr)); const Register iffalsereg = findRegFor(iffalse, GpRegs & ~rmask(rr));
if (op == LIR_cmov) { switch (condval->opcode()) {
switch (condval->opcode()) { // note that these are all opposites...
// note that these are all opposites... case LIR_eq: MOVNE(rr, iffalsereg); break;
case LIR_eq: MOVNE(rr, iffalsereg); break; case LIR_ov: MOVNO(rr, iffalsereg); break;
case LIR_ov: MOVNO(rr, iffalsereg); break; case LIR_cs: MOVNC(rr, iffalsereg); break;
case LIR_cs: MOVNC(rr, iffalsereg); break; case LIR_lt: MOVGE(rr, iffalsereg); break;
case LIR_lt: MOVGE(rr, iffalsereg); break; case LIR_le: MOVG(rr, iffalsereg); break;
case LIR_le: MOVG(rr, iffalsereg); break; case LIR_gt: MOVLE(rr, iffalsereg); break;
case LIR_gt: MOVLE(rr, iffalsereg); break; case LIR_ge: MOVL(rr, iffalsereg); break;
case LIR_ge: MOVL(rr, iffalsereg); break; case LIR_ult: MOVAE(rr, iffalsereg); break;
case LIR_ult: MOVAE(rr, iffalsereg); break; case LIR_ule: MOVA(rr, iffalsereg); break;
case LIR_ule: MOVA(rr, iffalsereg); break; case LIR_ugt: MOVBE(rr, iffalsereg); break;
case LIR_ugt: MOVBE(rr, iffalsereg); break; case LIR_uge: MOVB(rr, iffalsereg); break;
case LIR_uge: MOVB(rr, iffalsereg); break; default: debug_only( NanoAssert(0) ); break;
default: debug_only( NanoAssert(0) ); break;
}
} else if (op == LIR_qcmov) {
NanoAssert(0);
} }
/*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr); /*const Register iftruereg =*/ findSpecificRegFor(iftrue, rr);
asm_cmp(condval); asm_cmp(condval);