mirror of
https://gitlab.winehq.org/wine/wine-gecko.git
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Bug 851880 - Build OdinMonkey on more Unices. r=luke
This commit is contained in:
Jan Beich
parent
8341ce8b46
commit
7c559477dc
@ -17,8 +17,7 @@
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// Don't panic, mobile support is coming soon.
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#if defined(JS_ION) && \
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!defined(ANDROID) && \
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(defined(JS_CPU_X86) || defined(JS_CPU_X64)) && \
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(defined(__linux__) || defined(XP_WIN) || defined(XP_MACOSX))
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(defined(JS_CPU_X86) || defined(JS_CPU_X64))
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# define JS_ASMJS
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#endif
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@ -18,6 +18,120 @@ using namespace js::ion;
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#ifdef JS_ASMJS
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#if defined(XP_WIN)
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# define XMM_sig(p,i) ((p)->Xmm##i)
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# define EIP_sig(p) ((p)->Eip)
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# define RIP_sig(p) ((p)->Rip)
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# define RAX_sig(p) ((p)->Rax)
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# define RCX_sig(p) ((p)->Rcx)
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# define RDX_sig(p) ((p)->Rdx)
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# define RBX_sig(p) ((p)->Rbx)
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# define RSP_sig(p) ((p)->Rsp)
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# define RBP_sig(p) ((p)->Rbp)
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# define RSI_sig(p) ((p)->Rsi)
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# define RDI_sig(p) ((p)->Rdi)
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# define R8_sig(p) ((p)->R8)
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# define R9_sig(p) ((p)->R9)
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# define R10_sig(p) ((p)->R10)
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# define R11_sig(p) ((p)->R11)
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# define R12_sig(p) ((p)->R12)
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# define R13_sig(p) ((p)->R13)
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# define R14_sig(p) ((p)->R14)
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# define R15_sig(p) ((p)->R15)
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#elif defined(__OpenBSD__)
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# define XMM_sig(p,i) ((p)->sc_fpstate->fx_xmm[i])
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# define EIP_sig(p) ((p)->sc_eip)
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# define RIP_sig(p) ((p)->sc_rip)
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# define RAX_sig(p) ((p)->sc_rax)
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# define RCX_sig(p) ((p)->sc_rcx)
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# define RDX_sig(p) ((p)->sc_rdx)
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# define RBX_sig(p) ((p)->sc_rbx)
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# define RSP_sig(p) ((p)->sc_rsp)
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# define RBP_sig(p) ((p)->sc_rbp)
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# define RSI_sig(p) ((p)->sc_rsi)
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# define RDI_sig(p) ((p)->sc_rdi)
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# define R8_sig(p) ((p)->sc_r8)
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# define R9_sig(p) ((p)->sc_r9)
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# define R10_sig(p) ((p)->sc_r10)
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# define R11_sig(p) ((p)->sc_r11)
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# define R12_sig(p) ((p)->sc_r12)
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# define R13_sig(p) ((p)->sc_r13)
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# define R14_sig(p) ((p)->sc_r14)
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# define R15_sig(p) ((p)->sc_r15)
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#elif defined(__linux__) || defined(SOLARIS)
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# if defined(__linux__)
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# define XMM_sig(p,i) ((p)->uc_mcontext.fpregs->_xmm[i])
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# else
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# define XMM_sig(p,i) ((p)->uc_mcontext.fpregs.fp_reg_set.fpchip_state.xmm[i])
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# endif
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# define EIP_sig(p) ((p)->uc_mcontext.gregs[REG_EIP])
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# define RIP_sig(p) ((p)->uc_mcontext.gregs[REG_RIP])
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# define RAX_sig(p) ((p)->uc_mcontext.gregs[REG_RAX])
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# define RCX_sig(p) ((p)->uc_mcontext.gregs[REG_RCX])
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# define RDX_sig(p) ((p)->uc_mcontext.gregs[REG_RDX])
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# define RBX_sig(p) ((p)->uc_mcontext.gregs[REG_RBX])
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# define RSP_sig(p) ((p)->uc_mcontext.gregs[REG_RSP])
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# define RBP_sig(p) ((p)->uc_mcontext.gregs[REG_RBP])
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# define RSI_sig(p) ((p)->uc_mcontext.gregs[REG_RSI])
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# define RDI_sig(p) ((p)->uc_mcontext.gregs[REG_RDI])
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# define R8_sig(p) ((p)->uc_mcontext.gregs[REG_R8])
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# define R9_sig(p) ((p)->uc_mcontext.gregs[REG_R9])
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# define R10_sig(p) ((p)->uc_mcontext.gregs[REG_R10])
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# define R11_sig(p) ((p)->uc_mcontext.gregs[REG_R11])
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# define R12_sig(p) ((p)->uc_mcontext.gregs[REG_R12])
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# define R13_sig(p) ((p)->uc_mcontext.gregs[REG_R13])
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# define R14_sig(p) ((p)->uc_mcontext.gregs[REG_R14])
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# define R15_sig(p) ((p)->uc_mcontext.gregs[REG_R15])
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#elif defined(__NetBSD__)
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# define XMM_sig(p,i) (((struct fxsave64 *)(p)->uc_mcontext.__fpregs)->fx_xmm[i])
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# define EIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_EIP])
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# define RIP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RIP])
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# define RAX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RAX])
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# define RCX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RCX])
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# define RDX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RDX])
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# define RBX_sig(p) ((p)->uc_mcontext.__gregs[_REG_RBX])
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# define RSP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RSP])
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# define RBP_sig(p) ((p)->uc_mcontext.__gregs[_REG_RBP])
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# define RSI_sig(p) ((p)->uc_mcontext.__gregs[_REG_RSI])
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# define RDI_sig(p) ((p)->uc_mcontext.__gregs[_REG_RDI])
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# define R8_sig(p) ((p)->uc_mcontext.__gregs[_REG_R8])
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# define R9_sig(p) ((p)->uc_mcontext.__gregs[_REG_R9])
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# define R10_sig(p) ((p)->uc_mcontext.__gregs[_REG_R10])
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# define R11_sig(p) ((p)->uc_mcontext.__gregs[_REG_R11])
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# define R12_sig(p) ((p)->uc_mcontext.__gregs[_REG_R12])
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# define R13_sig(p) ((p)->uc_mcontext.__gregs[_REG_R13])
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# define R14_sig(p) ((p)->uc_mcontext.__gregs[_REG_R14])
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# define R15_sig(p) ((p)->uc_mcontext.__gregs[_REG_R15])
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#elif defined(__DragonFly__) || defined(__FreeBSD__)
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# if defined(__DragonFly__)
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# define XMM_sig(p,i) (((union savefpu *)(p)->uc_mcontext.mc_fpregs)->sv_xmm.sv_xmm[i])
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# else
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# define XMM_sig(p,i) (((struct savefpu *)(p)->uc_mcontext.mc_fpstate)->sv_xmm[i])
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# endif
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# define EIP_sig(p) ((p)->uc_mcontext.mc_eip)
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# define RIP_sig(p) ((p)->uc_mcontext.mc_rip)
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# define RAX_sig(p) ((p)->uc_mcontext.mc_rax)
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# define RCX_sig(p) ((p)->uc_mcontext.mc_rcx)
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# define RDX_sig(p) ((p)->uc_mcontext.mc_rdx)
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# define RBX_sig(p) ((p)->uc_mcontext.mc_rbx)
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# define RSP_sig(p) ((p)->uc_mcontext.mc_rsp)
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# define RBP_sig(p) ((p)->uc_mcontext.mc_rbp)
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# define RSI_sig(p) ((p)->uc_mcontext.mc_rsi)
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# define RDI_sig(p) ((p)->uc_mcontext.mc_rdi)
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# define R8_sig(p) ((p)->uc_mcontext.mc_r8)
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# define R9_sig(p) ((p)->uc_mcontext.mc_r9)
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# define R10_sig(p) ((p)->uc_mcontext.mc_r10)
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# define R11_sig(p) ((p)->uc_mcontext.mc_r11)
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# define R12_sig(p) ((p)->uc_mcontext.mc_r12)
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# define R13_sig(p) ((p)->uc_mcontext.mc_r13)
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# define R14_sig(p) ((p)->uc_mcontext.mc_r14)
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# define R15_sig(p) ((p)->uc_mcontext.mc_r15)
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#elif defined(XP_MACOSX)
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// Mach requires special treatment.
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#else
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# error "Don't know how to read/write to the thread state via the mcontext_t."
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#endif
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// For platforms where the signal/exception handler runs on the same
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// thread/stack as the victim (Unix and Windows), we can use TLS to find any
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// currently executing asm.js code.
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@ -144,16 +258,37 @@ LookupHeapAccess(const AsmJSModule &module, uint8_t *pc)
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# if defined(XP_WIN)
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# include "jswin.h"
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# else
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# include <signal.h>
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# include <sys/mman.h>
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# endif
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# if defined(__FreeBSD__)
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# include <sys/ucontext.h> // for ucontext_t, mcontext_t
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# endif
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# if defined(JS_CPU_X64)
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# if defined(__DragonFly__)
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# include <machine/npx.h> // for union savefpu
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# elif defined(__FreeBSD__) || defined(__OpenBSD__)
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# include <machine/fpu.h> // for struct savefpu/fxsave64
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# endif
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# endif
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# if !defined(XP_WIN)
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# define CONTEXT ucontext_t
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# endif
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# if !defined(XP_MACOSX)
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static uint8_t **
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ContextToPC(PCONTEXT context)
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ContextToPC(CONTEXT *context)
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{
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# if defined(JS_CPU_X64)
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JS_STATIC_ASSERT(sizeof(context->Rip) == sizeof(void*));
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return reinterpret_cast<uint8_t**>(&context->Rip);
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JS_STATIC_ASSERT(sizeof(RIP_sig(context)) == sizeof(void*));
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return reinterpret_cast<uint8_t**>(&RIP_sig(context));
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# else
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JS_STATIC_ASSERT(sizeof(context->Eip) == sizeof(void*));
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return reinterpret_cast<uint8_t**>(&context->Eip);
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JS_STATIC_ASSERT(sizeof(EIP_sig(context)) == sizeof(void*));
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return reinterpret_cast<uint8_t**>(&EIP_sig(context));
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# endif
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}
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@ -163,47 +298,50 @@ SetRegisterToCoercedUndefined(CONTEXT *context, bool isFloat32, AnyRegister reg)
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{
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if (reg.isFloat()) {
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switch (reg.fpu().code()) {
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case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, &context->Xmm0); break;
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case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, &context->Xmm1); break;
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case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, &context->Xmm2); break;
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case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, &context->Xmm3); break;
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case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, &context->Xmm4); break;
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case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, &context->Xmm5); break;
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case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, &context->Xmm6); break;
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case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, &context->Xmm7); break;
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case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, &context->Xmm8); break;
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case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, &context->Xmm9); break;
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case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, &context->Xmm10); break;
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case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, &context->Xmm11); break;
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case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, &context->Xmm12); break;
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case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, &context->Xmm13); break;
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case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, &context->Xmm14); break;
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case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, &context->Xmm15); break;
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case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 0)); break;
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case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 1)); break;
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case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 2)); break;
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case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 3)); break;
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case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 4)); break;
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case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 5)); break;
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case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 6)); break;
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case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 7)); break;
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case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 8)); break;
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case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 9)); break;
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case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 10)); break;
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case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 11)); break;
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case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 12)); break;
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case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 13)); break;
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case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 14)); break;
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case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, &XMM_sig(context, 15)); break;
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default: MOZ_CRASH();
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}
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} else {
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switch (reg.gpr().code()) {
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case JSC::X86Registers::eax: context->Rax = 0; break;
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case JSC::X86Registers::ecx: context->Rcx = 0; break;
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case JSC::X86Registers::edx: context->Rdx = 0; break;
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case JSC::X86Registers::ebx: context->Rbx = 0; break;
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case JSC::X86Registers::esp: context->Rsp = 0; break;
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case JSC::X86Registers::ebp: context->Rbp = 0; break;
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case JSC::X86Registers::esi: context->Rsi = 0; break;
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case JSC::X86Registers::edi: context->Rdi = 0; break;
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case JSC::X86Registers::r8: context->R8 = 0; break;
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case JSC::X86Registers::r9: context->R9 = 0; break;
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case JSC::X86Registers::r10: context->R10 = 0; break;
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case JSC::X86Registers::r11: context->R11 = 0; break;
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case JSC::X86Registers::r12: context->R12 = 0; break;
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case JSC::X86Registers::r13: context->R13 = 0; break;
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case JSC::X86Registers::r14: context->R14 = 0; break;
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case JSC::X86Registers::r15: context->R15 = 0; break;
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case JSC::X86Registers::eax: RAX_sig(context) = 0; break;
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case JSC::X86Registers::ecx: RCX_sig(context) = 0; break;
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case JSC::X86Registers::edx: RDX_sig(context) = 0; break;
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case JSC::X86Registers::ebx: RBX_sig(context) = 0; break;
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case JSC::X86Registers::esp: RSP_sig(context) = 0; break;
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case JSC::X86Registers::ebp: RBP_sig(context) = 0; break;
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case JSC::X86Registers::esi: RSI_sig(context) = 0; break;
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case JSC::X86Registers::edi: RDI_sig(context) = 0; break;
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case JSC::X86Registers::r8: R8_sig(context) = 0; break;
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case JSC::X86Registers::r9: R9_sig(context) = 0; break;
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case JSC::X86Registers::r10: R10_sig(context) = 0; break;
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case JSC::X86Registers::r11: R11_sig(context) = 0; break;
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case JSC::X86Registers::r12: R12_sig(context) = 0; break;
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case JSC::X86Registers::r13: R13_sig(context) = 0; break;
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case JSC::X86Registers::r14: R14_sig(context) = 0; break;
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case JSC::X86Registers::r15: R15_sig(context) = 0; break;
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default: MOZ_CRASH();
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}
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}
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}
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# endif
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# endif // JS_CPU_X64
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# endif // !XP_MACOSX
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# if defined(XP_WIN)
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static bool
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HandleException(PEXCEPTION_POINTERS exception)
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@ -289,7 +427,6 @@ AsmJSExceptionHandler(LPEXCEPTION_POINTERS exception)
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}
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# elif defined(XP_MACOSX)
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# include <sys/mman.h>
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# include <mach/exc.h>
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static uint8_t **
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@ -615,70 +752,6 @@ AsmJSMachExceptionHandler::install(JSRuntime *rt)
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}
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# else // If not Windows or Mac, assume Unix
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# include <signal.h>
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# include <sys/mman.h>
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// Unfortunately, we still need OS-specific code to read/write to the thread
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// state via the mcontext_t.
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static uint8_t **
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ContextToPC(mcontext_t &context)
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{
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# if defined(JS_CPU_X86)
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JS_STATIC_ASSERT(sizeof(context.gregs[REG_EIP]) == sizeof(void*));
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return reinterpret_cast<uint8_t**>(&context.gregs[REG_EIP]);
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# else
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JS_STATIC_ASSERT(sizeof(context.gregs[REG_RIP]) == sizeof(void*));
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return reinterpret_cast<uint8_t**>(&context.gregs[REG_RIP]);
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# endif
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}
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# if defined(JS_CPU_X64)
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static void
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SetRegisterToCoercedUndefined(mcontext_t &context, bool isFloat32, AnyRegister reg)
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{
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if (reg.isFloat()) {
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switch (reg.fpu().code()) {
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case JSC::X86Registers::xmm0: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[0]); break;
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case JSC::X86Registers::xmm1: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[1]); break;
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case JSC::X86Registers::xmm2: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[2]); break;
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case JSC::X86Registers::xmm3: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[3]); break;
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case JSC::X86Registers::xmm4: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[4]); break;
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case JSC::X86Registers::xmm5: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[5]); break;
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case JSC::X86Registers::xmm6: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[6]); break;
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case JSC::X86Registers::xmm7: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[7]); break;
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case JSC::X86Registers::xmm8: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[8]); break;
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case JSC::X86Registers::xmm9: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[9]); break;
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case JSC::X86Registers::xmm10: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[10]); break;
|
||||
case JSC::X86Registers::xmm11: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[11]); break;
|
||||
case JSC::X86Registers::xmm12: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[12]); break;
|
||||
case JSC::X86Registers::xmm13: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[13]); break;
|
||||
case JSC::X86Registers::xmm14: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[14]); break;
|
||||
case JSC::X86Registers::xmm15: SetXMMRegToNaN(isFloat32, &context.fpregs->_xmm[15]); break;
|
||||
default: MOZ_CRASH();
|
||||
}
|
||||
} else {
|
||||
switch (reg.gpr().code()) {
|
||||
case JSC::X86Registers::eax: context.gregs[REG_RAX] = 0; break;
|
||||
case JSC::X86Registers::ecx: context.gregs[REG_RCX] = 0; break;
|
||||
case JSC::X86Registers::edx: context.gregs[REG_RDX] = 0; break;
|
||||
case JSC::X86Registers::ebx: context.gregs[REG_RBX] = 0; break;
|
||||
case JSC::X86Registers::esp: context.gregs[REG_RSP] = 0; break;
|
||||
case JSC::X86Registers::ebp: context.gregs[REG_RBP] = 0; break;
|
||||
case JSC::X86Registers::esi: context.gregs[REG_RSI] = 0; break;
|
||||
case JSC::X86Registers::edi: context.gregs[REG_RDI] = 0; break;
|
||||
case JSC::X86Registers::r8: context.gregs[REG_R8] = 0; break;
|
||||
case JSC::X86Registers::r9: context.gregs[REG_R9] = 0; break;
|
||||
case JSC::X86Registers::r10: context.gregs[REG_R10] = 0; break;
|
||||
case JSC::X86Registers::r11: context.gregs[REG_R11] = 0; break;
|
||||
case JSC::X86Registers::r12: context.gregs[REG_R12] = 0; break;
|
||||
case JSC::X86Registers::r13: context.gregs[REG_R13] = 0; break;
|
||||
case JSC::X86Registers::r14: context.gregs[REG_R14] = 0; break;
|
||||
case JSC::X86Registers::r15: context.gregs[REG_R15] = 0; break;
|
||||
default: MOZ_CRASH();
|
||||
}
|
||||
}
|
||||
}
|
||||
# endif
|
||||
|
||||
// Be very cautious and default to not handling; we don't want to accidentally
|
||||
// silence real crashes from real bugs.
|
||||
@ -689,7 +762,7 @@ HandleSignal(int signum, siginfo_t *info, void *ctx)
|
||||
if (!activation)
|
||||
return false;
|
||||
|
||||
mcontext_t &context = reinterpret_cast<ucontext_t*>(ctx)->uc_mcontext;
|
||||
CONTEXT *context = (CONTEXT *)ctx;
|
||||
uint8_t **ppc = ContextToPC(context);
|
||||
uint8_t *pc = *ppc;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user