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here, have a Thumb back-end
This commit is contained in:
shaver@mozilla.org
parent
5089017f47
commit
6f69036887
972
js/src/nanojit/NativeThumb.cpp
Normal file
972
js/src/nanojit/NativeThumb.cpp
Normal file
@ -0,0 +1,972 @@
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/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: t; tab-width: 4 -*- */
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is [Open Source Virtual Machine].
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*
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* The Initial Developer of the Original Code is
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* Adobe System Incorporated.
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* Portions created by the Initial Developer are Copyright (C) 2004-2007
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Adobe AS3 Team
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either the GNU General Public License Version 2 or later (the "GPL"), or
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* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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* in which case the provisions of the GPL or the LGPL are applicable instead
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* of those above. If you wish to allow use of your version of this file only
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* under the terms of either the GPL or the LGPL, and not to allow others to
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* use your version of this file under the terms of the MPL, indicate your
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* decision by deleting the provisions above and replace them with the notice
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||||
* and other provisions required by the GPL or the LGPL. If you do not delete
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||||
* the provisions above, a recipient may use your version of this file under
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* the terms of any one of the MPL, the GPL or the LGPL.
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*
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* ***** END LICENSE BLOCK ***** */
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#include "nanojit.h"
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#ifdef UNDER_CE
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#include <cmnintrin.h>
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#endif
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namespace nanojit
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{
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#ifdef FEATURE_NANOJIT
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#ifdef NJ_VERBOSE
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const char* regNames[] = {"r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","IP","SP","LR","PC"};
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#endif
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const Register Assembler::argRegs[] = { R0, R1, R2, R3 };
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const Register Assembler::retRegs[] = { R0, R1 };
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void Assembler::nInit(AvmCore*)
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{
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#ifdef NJ_THUMB_JIT
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// Thumb mode does not have conditional move, alas
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has_cmov = false;
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#else
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// all ARMs have conditional move
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has_cmov = true;
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#endif
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}
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NIns* Assembler::genPrologue(RegisterMask needSaving)
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{
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/**
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* Prologue
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*/
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// NJ_RESV_OFFSET is space at the top of the stack for us
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// to use for parameter passing (8 bytes at the moment)
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uint32_t stackNeeded = 4 * _activation.highwatermark + NJ_STACK_OFFSET;
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uint32_t savingCount = 0;
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uint32_t savingMask = 0;
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#if defined(NJ_THUMB_JIT)
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savingCount = 5; // R4-R7, LR
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savingMask = 0xF0;
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(void)needSaving;
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#else
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savingCount = 9; //R4-R10,R11,LR
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savingMask = SavedRegs | rmask(FRAME_PTR);
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(void)needSaving;
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#endif
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// so for alignment purposes we've pushed return addr, fp, and savingCount registers
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uint32_t stackPushed = 4 * (2+savingCount);
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uint32_t aligned = alignUp(stackNeeded + stackPushed, NJ_ALIGN_STACK);
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int32_t amt = aligned - stackPushed;
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// Make room on stack for what we are doing
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if (amt)
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#ifdef NJ_THUMB_JIT
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{
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// largest value is 508 (7-bits << 2)
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if (amt>508)
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{
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int size = 508;
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while (size>0)
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{
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SUBi(SP, size);
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amt -= size;
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size = amt;
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if (size>508)
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size=508;
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}
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}
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else
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SUBi(SP, amt);
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}
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#else
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{
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SUBi(SP, amt);
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}
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#endif
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verbose_only( verbose_outputf(" %p:",_nIns); )
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verbose_only( verbose_output(" patch entry"); )
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NIns *patchEntry = _nIns;
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MR(FRAME_PTR, SP);
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PUSH_mask(savingMask|rmask(LR));
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return patchEntry;
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}
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GuardRecord* Assembler::nFragExit(LInsp guard)
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{
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SideExit* exit = guard->exit();
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Fragment *frag = exit->target;
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GuardRecord *lr;
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if (frag && frag->fragEntry)
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{
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JMP(frag->fragEntry);
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lr = 0;
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}
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else
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{
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// target doesn't exit yet. emit jump to epilog, and set up to patch later.
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lr = placeGuardRecord(guard);
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BL(_epilogue);
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lr->jmp = _nIns;
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}
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// pop the stack frame first
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MR(SP, FRAME_PTR);
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#ifdef NJ_VERBOSE
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if (_frago->core()->config.show_stats) {
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// load R1 with Fragment *fromFrag, target fragment
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// will make use of this when calling fragenter().
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int fromfrag = int(exit->from);
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LDi(argRegs[1], fromfrag);
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}
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#endif
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// return value is GuardRecord*
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LDi(R2, int(lr));
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// if/when we patch this exit to jump over to another fragment,
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// that fragment will need its parameters set up just like ours.
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LInsp param0 = _thisfrag->param0;
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Register state = findSpecificRegFor(param0, Register(param0->imm8()));
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// update InterpState
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NanoAssert(offsetof(avmplus::InterpState,f) == 0);
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NanoAssert(offsetof(avmplus::InterpState,ip) == 4);
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NanoAssert(offsetof(avmplus::InterpState,sp) == 8);
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NanoAssert(offsetof(avmplus::InterpState,rp) == 12);
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NanoAssert(sizeof(avmplus::InterpState) == 16);
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RegisterMask ptrs = 0x1e; // { R1-R4 }
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SUBi(state, 16);
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STMIA(state, ptrs);
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if (exit->rp_adj) ADDi(R4, exit->rp_adj);
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if (exit->sp_adj) ADDi(R3, exit->sp_adj);
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if (exit->ip_adj) ADDi(R2, exit->ip_adj);
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if (exit->f_adj) ADDi(R1, exit->f_adj);
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SUBi(state, 16);
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LDMIA(state, ptrs);
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return lr;
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}
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NIns* Assembler::genEpilogue(RegisterMask restore)
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{
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#ifdef NJ_THUMB_JIT
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(void)restore;
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if (false) {
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// interworking
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BX(R3); // return
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POP(R3); // POP LR into R3
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POP_mask(0xF0); // {R4-R7}
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} else {
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// return to Thumb caller
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POP_mask(0xF0|rmask(PC));
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}
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MR(R0,R2); // return LinkRecord*
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return _nIns;
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#else
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BX(LR); // return
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MR(R0,R2); // return LinkRecord*
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RegisterMask savingMask = restore | rmask(FRAME_PTR) | rmask(LR);
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POP_mask(savingMask); // regs
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return _nIns;
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#endif
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}
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void Assembler::nArgEmitted(const CallInfo* call, uint32_t stackSlotCount, uint32_t iargs, uint32_t fargs)
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{
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#if 1
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(void)call;
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(void)stackSlotCount;
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(void)iargs;
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(void)fargs;
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#else
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// see if we have finished emitting all args. If so then make sure the
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// new stack pointer is NJ_ALIGN_STACK aligned
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if (iargs == call->iargs && fargs == call->fargs)
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{
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int32_t istack = iargs;
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istack -= 4;
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if (istack<=0)
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return; // nothing on stack
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const int32_t size = 4*stackSlotCount;
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const int32_t extra = alignUp(size, NJ_ALIGN_STACK) - size;
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if (extra > 0)
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SUBi(SP, extra);
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}
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#endif
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}
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void Assembler::nPostCallCleanup(const CallInfo* call)
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{
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#if 1
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(void)call;
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#else
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int32_t istack = call->iargs;
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int32_t fstack = call->fargs;
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istack -= 4; // first 4 4B args are in registers
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if (istack <= 0)
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{
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return; // nothing on stack
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//istack = 0;
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//if (fstack == 0)
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//return; // only using ECX/EDX nothing passed on the stack so no cleanup needed
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}
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const int32_t size = 4*istack + 8*fstack; // actual stack space used
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NanoAssert( size > 0 );
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const int32_t extra = alignUp(size, NJ_ALIGN_STACK);
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// stack re-alignment
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// only pop our adjustment amount since callee pops args in FASTCALL mode
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if (extra > 0)
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{ ADDi(SP, extra); }
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#endif
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return;
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}
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void Assembler::nMarkExecute(Page* page, int32_t count, bool enable)
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{
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#ifdef UNDER_CE
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DWORD dwOld;
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VirtualProtect(page, NJ_PAGE_SIZE, PAGE_EXECUTE_READWRITE, &dwOld);
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#endif
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(void)page;
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(void)count;
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(void)enable;
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}
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Register Assembler::nRegisterAllocFromSet(int set)
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{
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#ifdef NJ_THUMB_JIT
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// need to implement faster way
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int i=0;
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while (!(set & rmask((Register)i)))
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i ++;
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_allocator.free &= ~rmask((Register)i);
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return (Register) i;
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#else
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// Note: The clz instruction only works on armv5 and up.
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Register r;
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#ifndef UNDER_CE
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register int i;
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asm("clz %0,%1" : "=r" (i) : "r" (set));
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i = 31-i;
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regs.free &= ~rmask(i);
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#else
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r = (Register)_CountLeadingZeros(set);
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r = (Register)(31-r);
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_allocator.free &= ~rmask(r);
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#endif
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return r;
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#endif
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}
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void Assembler::nRegisterResetAll(RegAlloc& a)
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{
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// add scratch registers to our free list for the allocator
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a.clear();
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a.used = 0;
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a.free = rmask(R0) | rmask(R1) | rmask(R2) | rmask(R3) | rmask(R4) | rmask(R5);
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debug_only(a.managed = a.free);
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}
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void Assembler::nPatchBranch(NIns* branch, NIns* target)
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{
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// Patch the jump in a loop
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// This is ALWAYS going to be a long branch (using the BL instruction)
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// Which is really 2 instructions, so we need to modify both
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// branch+2 because PC is always 2 instructions ahead on ARM/Thumb
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int32_t offset = int(target) - int(branch+2);
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//printf("---patching branch at %X to location %X (%d)\n", branch, target, offset);
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#ifdef NJ_THUMB_JIT
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NanoAssert(-(1<<21) <= offset && offset < (1<<21));
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*branch++ = (NIns)(0xF000 | (offset>>12)&0x7FF);
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*branch = (NIns)(0xF800 | (offset>>1)&0x7FF);
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#else
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// ARM goodness, using unconditional B
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*branch = (NIns)( COND_AL | (0xA<<24) | ((offset >>2)& 0xFFFFFF) );
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#endif
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}
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RegisterMask Assembler::hint(LIns* i, RegisterMask allow /* = ~0 */)
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{
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uint32_t op = i->opcode();
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int prefer = ~0;
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if (op==LIR_call || op==LIR_fcall)
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prefer = rmask(R0);
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else if (op == LIR_callh)
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prefer = rmask(R1);
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else if (op == LIR_param)
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prefer = rmask(imm2register(i->imm8()));
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if (_allocator.free & allow & prefer)
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allow &= prefer;
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return allow;
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}
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void Assembler::asm_qjoin(LIns *ins)
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{
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int d = findMemFor(ins);
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AvmAssert(d);
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LIns* lo = ins->oprnd1();
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LIns* hi = ins->oprnd2();
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Register r = findRegFor(hi, GpRegs);
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ST(FP, d+4, r);
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// okay if r gets recycled.
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r = findRegFor(lo, GpRegs);
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ST(FP, d, r);
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freeRsrcOf(ins, false); // if we had a reg in use, emit a ST to flush it to mem
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}
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void Assembler::asm_store32(LIns *value, int dr, LIns *base)
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{
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// make sure what is in a register
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Reservation *rA, *rB;
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findRegFor2(GpRegs, value, rA, base, rB);
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Register ra = rA->reg;
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Register rb = rB->reg;
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ST(rb, dr, ra);
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}
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void Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
|
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{
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(void)resv;
|
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int d = findMemFor(i);
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LD(r, d, FP);
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verbose_only(if (_verbose) {
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outputf(" restore %s",_thisfrag->lirbuf->names->formatRef(i));
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})
|
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}
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void Assembler::asm_spill(LInsp i, Reservation *resv, bool pop)
|
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{
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(void)i;
|
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(void)pop;
|
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if (resv->arIndex)
|
||||
{
|
||||
int d = disp(resv);
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||||
// save to spill location
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Register rr = resv->reg;
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ST(FP, d, rr);
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verbose_only(if (_verbose){
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outputf(" spill %s",_thisfrag->lirbuf->names->formatRef(i));
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})
|
||||
}
|
||||
}
|
||||
|
||||
void Assembler::asm_load64(LInsp ins)
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{
|
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LIns* base = ins->oprnd1();
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int db = ins->oprnd2()->constval();
|
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Reservation *resv = getresv(ins);
|
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int dr = disp(resv);
|
||||
NanoAssert(resv->reg == UnknownReg && dr != 0);
|
||||
|
||||
Register rb = findRegFor(base, GpRegs);
|
||||
resv->reg = UnknownReg;
|
||||
asm_mmq(FP, dr, rb, db);
|
||||
freeRsrcOf(ins, false);
|
||||
}
|
||||
|
||||
void Assembler::asm_store64(LInsp value, int dr, LInsp base)
|
||||
{
|
||||
int da = findMemFor(value);
|
||||
Register rb = findRegFor(base, GpRegs);
|
||||
asm_mmq(rb, dr, FP, da);
|
||||
}
|
||||
|
||||
/**
|
||||
* copy 64 bits: (rd+dd) <- (rs+ds)
|
||||
*/
|
||||
void Assembler::asm_mmq(Register rd, int dd, Register rs, int ds)
|
||||
{
|
||||
// value is either a 64bit struct or maybe a float
|
||||
// that isn't live in an FPU reg. Either way, don't
|
||||
// put it in an FPU reg just to load & store it.
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||||
// get a scratch reg
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||||
Register t = registerAlloc(GpRegs & ~(rmask(rd)|rmask(rs)));
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_allocator.addFree(t);
|
||||
ST(rd, dd+4, t);
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||||
LD(t, ds+4, rs);
|
||||
ST(rd, dd, t);
|
||||
LD(t, ds, rs);
|
||||
}
|
||||
|
||||
void Assembler::asm_pusharg(LInsp p)
|
||||
{
|
||||
// arg goes on stack
|
||||
Reservation* rA = getresv(p);
|
||||
if (rA == 0)
|
||||
{
|
||||
Register ra = findRegFor(p, GpRegs);
|
||||
ST(SP,0,ra);
|
||||
}
|
||||
else if (rA->reg == UnknownReg)
|
||||
{
|
||||
ST(SP,0,Scratch);
|
||||
LD(Scratch,disp(rA),FP);
|
||||
}
|
||||
else
|
||||
{
|
||||
ST(SP,0,rA->reg);
|
||||
}
|
||||
}
|
||||
|
||||
NIns* Assembler::asm_adjustBranch(NIns* at, NIns* target)
|
||||
{
|
||||
NIns* save = _nIns;
|
||||
#ifdef NJ_THUMB_JIT
|
||||
NIns* was = (NIns*) (((((*(at+2))&0x7ff)<<12) | (((*(at+1))&0x7ff)<<1)) + (at-2+2));
|
||||
_nIns = at + 2;
|
||||
#else
|
||||
NIns* was = (NIns*) (((*at&0xFFFFFF)<<2));
|
||||
_nIns = at + 1;
|
||||
#endif
|
||||
BL(target);
|
||||
_nIns = save;
|
||||
|
||||
#ifdef UNDER_CE
|
||||
// we changed the code, so we need to do this (sadly)
|
||||
FlushInstructionCache(GetCurrentProcess(), NULL, NULL);
|
||||
#endif
|
||||
return was;
|
||||
}
|
||||
|
||||
void Assembler::nativePageReset()
|
||||
{
|
||||
#ifdef NJ_THUMB_JIT
|
||||
_nPool = 0;
|
||||
_nSlot = 0;
|
||||
_nExitPool = 0;
|
||||
_nExitSlot = 0;
|
||||
#else
|
||||
_nSlot = 0;
|
||||
_nExitSlot = 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
void Assembler::nativePageSetup()
|
||||
{
|
||||
if (!_nIns) _nIns = pageAlloc();
|
||||
if (!_nExitIns) _nExitIns = pageAlloc(true);
|
||||
//fprintf(stderr, "assemble onto %x exits into %x\n", (int)_nIns, (int)_nExitIns);
|
||||
|
||||
#ifdef NJ_THUMB_JIT
|
||||
if (!_nPool) {
|
||||
_nSlot = _nPool = (int*)_nIns;
|
||||
|
||||
// Make original pool at end of page. Currently
|
||||
// we are pointing off the end of the original page,
|
||||
// so back up 1+NJ_CPOOL_SIZE
|
||||
_nPool = (int*)((int)_nIns - (sizeof(int32_t)*NJ_CPOOL_SIZE));
|
||||
|
||||
// _nSlot points at last slot in pool (fill upwards)
|
||||
_nSlot = _nPool + (NJ_CPOOL_SIZE-1);
|
||||
|
||||
// Move _nIns to the top of the pool
|
||||
_nIns = (NIns*)_nPool;
|
||||
|
||||
// no branch needed since this follows the epilogue
|
||||
}
|
||||
#else
|
||||
if (!_nSlot)
|
||||
{
|
||||
// This needs to be done or the samepage macro gets confused
|
||||
_nIns--;
|
||||
_nExitIns--;
|
||||
|
||||
// constpool starts at top of page and goes down,
|
||||
// code starts at bottom of page and moves up
|
||||
_nSlot = (int*)(pageTop(_nIns)+1);
|
||||
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#ifdef NJ_THUMB_JIT
|
||||
|
||||
void Assembler::STi(Register b, int32_t d, int32_t v)
|
||||
{
|
||||
ST(b, d, Scratch);
|
||||
LDi(Scratch, v);
|
||||
}
|
||||
|
||||
bool isB11(NIns *target, NIns *cur)
|
||||
{
|
||||
NIns *br_base = (cur-1)+2;
|
||||
int br_off = int(target) - int(br_base);
|
||||
return (-(1<<11) <= br_off && br_off < (1<<11));
|
||||
}
|
||||
|
||||
void Assembler::underrunProtect(int bytes)
|
||||
{
|
||||
intptr_t u = bytes + 4;
|
||||
if (!samepage(_nIns-u, _nIns-1)) {
|
||||
NIns* target = _nIns;
|
||||
_nIns = pageAlloc(_inExit);
|
||||
// might be able to do a B instead of BL (save an instruction)
|
||||
if (isB11(target, _nIns))
|
||||
{
|
||||
NIns *br_base = (_nIns-1)+2;
|
||||
int br_off = int(target) - int(br_base);
|
||||
*(--_nIns) = (NIns)(0xE000 | ((br_off>>1)&0x7FF));
|
||||
}
|
||||
else
|
||||
{
|
||||
int offset = int(target)-int(_nIns-2+2);
|
||||
*(--_nIns) = (NIns)(0xF800 | ((offset>>1)&0x7FF) );
|
||||
*(--_nIns) = (NIns)(0xF000 | ((offset>>12)&0x7FF) );
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool isB22(NIns *target, NIns *cur)
|
||||
{
|
||||
int offset = int(target)-int(cur-2+2);
|
||||
return (-(1<<22) <= offset && offset < (1<<22));
|
||||
}
|
||||
|
||||
void Assembler::BL(NIns* target)
|
||||
{
|
||||
underrunProtect(4);
|
||||
NanoAssert(isB22(target,_nIns));
|
||||
int offset = int(target)-int(_nIns-2+2);
|
||||
*(--_nIns) = (NIns)(0xF800 | ((offset>>1)&0x7FF) );
|
||||
*(--_nIns) = (NIns)(0xF000 | ((offset>>12)&0x7FF) );
|
||||
asm_output2("bl %X offset=%d",(int)target, offset);
|
||||
}
|
||||
|
||||
|
||||
void Assembler::B(NIns *target)
|
||||
{
|
||||
underrunProtect(2);
|
||||
NanoAssert(isB11(target,_nIns));
|
||||
NIns *br_base = (_nIns-1)+2;
|
||||
int br_off = int(target) - int(br_base);
|
||||
NanoAssert(-(1<<11) <= br_off && br_off < (1<<11));
|
||||
*(--_nIns) = (NIns)(0xE000 | ((br_off>>1)&0x7FF));
|
||||
asm_output2("b %X offset=%d", (int)target, br_off);
|
||||
}
|
||||
|
||||
void Assembler::JMP(NIns *target)
|
||||
{
|
||||
underrunProtect(4);
|
||||
if (isB11(target,_nIns))
|
||||
B(target);
|
||||
else
|
||||
BL(target);
|
||||
}
|
||||
|
||||
void Assembler::PUSH_mask(RegisterMask mask)
|
||||
{
|
||||
NanoAssert((mask&(0xff|rmask(LR)))==mask);
|
||||
underrunProtect(2);
|
||||
if (mask & rmask(LR)) {
|
||||
mask &= ~rmask(LR);
|
||||
mask |= rmask(R8);
|
||||
}
|
||||
*(--_nIns) = (NIns)(0xB400 | mask);
|
||||
asm_output1("push {%x}", mask);
|
||||
}
|
||||
|
||||
void Assembler::POP(Register r)
|
||||
{
|
||||
underrunProtect(2);
|
||||
NanoAssert(((unsigned)r)<8 || r == PC);
|
||||
if (r == PC)
|
||||
r = R8;
|
||||
*(--_nIns) = (NIns)(0xBC00 | (1<<(r)));
|
||||
asm_output1("pop {%s}",gpn(r));
|
||||
}
|
||||
|
||||
void Assembler::POP_mask(RegisterMask mask)
|
||||
{
|
||||
NanoAssert((mask&(0xff|rmask(PC)))==mask);
|
||||
underrunProtect(2);
|
||||
if (mask & rmask(PC)) {
|
||||
mask &= ~rmask(PC);
|
||||
mask |= rmask(R8);
|
||||
}
|
||||
*(--_nIns) = (NIns)(0xBC00 | mask);
|
||||
asm_output1("pop {%x}", mask);
|
||||
}
|
||||
|
||||
void Assembler::MOVi(Register r, int32_t v)
|
||||
{
|
||||
NanoAssert(isU8(v));
|
||||
underrunProtect(2);
|
||||
*(--_nIns) = (NIns)(0x2000 | r<<8 | v);
|
||||
asm_output2("mov %s,#%d",gpn(r),v);
|
||||
}
|
||||
|
||||
void Assembler::LDi(Register r, int32_t v)
|
||||
{
|
||||
if (isU8(v)) {
|
||||
MOVi(r,v);
|
||||
} else if (isU8(-v)) {
|
||||
NEG(r);
|
||||
MOVi(r,-v);
|
||||
} else {
|
||||
underrunProtect(2);
|
||||
LD32_nochk(r, v);
|
||||
}
|
||||
}
|
||||
|
||||
void Assembler::B_cond(int c, NIns *target)
|
||||
{
|
||||
#ifdef NJ_VERBOSE
|
||||
static const char *ccname[] = { "eq","ne","hs","lo","mi","pl","vs","vc","hi","ls","ge","lt","gt","le","al","nv" };
|
||||
#endif
|
||||
|
||||
underrunProtect(6);
|
||||
int tt = int(target) - int(_nIns-1+2);
|
||||
if (tt < (1<<8) && tt >= -(1<<8)) {
|
||||
*(--_nIns) = (NIns)(0xD000 | ((c)<<8) | (tt>>1)&0xFF );
|
||||
asm_output3("b%s %X offset=%d", ccname[c], target, tt);
|
||||
} else {
|
||||
NIns *skip = _nIns;
|
||||
BL(target);
|
||||
c ^= 1;
|
||||
*(--_nIns) = (NIns)(0xD000 | c<<8 | 1 );
|
||||
asm_output2("b%s %X", ccname[c], skip);
|
||||
}
|
||||
}
|
||||
|
||||
void Assembler::STR_sp(int32_t offset, Register reg)
|
||||
{
|
||||
NanoAssert((offset&3)==0);// require natural alignment
|
||||
int32_t off = offset>>2;
|
||||
NanoAssert(isU8(off));
|
||||
underrunProtect(2);
|
||||
*(--_nIns) = (NIns)(0x9000 | ((reg)<<8) | off );
|
||||
asm_output3("str %s, %d(%s)", gpn(reg), offset, gpn(SP));
|
||||
}
|
||||
|
||||
void Assembler::STR_index(Register base, Register off, Register reg)
|
||||
{
|
||||
underrunProtect(2);
|
||||
*(--_nIns) = (NIns)(0x5000 | (off<<6) | (base<<3) | (reg));
|
||||
asm_output3("str %s,(%s+%s)",gpn(reg),gpn(base),gpn(off));
|
||||
}
|
||||
|
||||
void Assembler::STR_m(Register base, int32_t offset, Register reg)
|
||||
{
|
||||
NanoAssert(offset >= 0 && offset < 128 && (offset&3)==0);
|
||||
underrunProtect(2);
|
||||
int32_t off = offset>>2;
|
||||
*(--_nIns) = (NIns)(0x6000 | off<<6 | base<<3 | reg);
|
||||
asm_output3("str %s,%d(%s)", gpn(reg), offset, gpn(base));
|
||||
}
|
||||
|
||||
void Assembler::LDMIA(Register base, RegisterMask regs)
|
||||
{
|
||||
underrunProtect(2);
|
||||
NanoAssert((regs&rmask(base))==0 && isU8(regs));
|
||||
*(--_nIns) = (NIns)(0xC800 | base<<8 | regs);
|
||||
asm_output2("ldmia %s!,{%x}", gpn(base), regs);
|
||||
}
|
||||
|
||||
void Assembler::STMIA(Register base, RegisterMask regs)
|
||||
{
|
||||
underrunProtect(2);
|
||||
NanoAssert((regs&rmask(base))==0 && isU8(regs));
|
||||
*(--_nIns) = (NIns)(0xC000 | base<<8 | regs);
|
||||
asm_output2("stmia %s!,{%x}", gpn(base), regs);
|
||||
}
|
||||
|
||||
void Assembler::ST(Register base, int32_t offset, Register reg)
|
||||
{
|
||||
NanoAssert((offset&3)==0);// require natural alignment
|
||||
int off = offset>>2;
|
||||
if (base==SP) {
|
||||
STR_sp(offset, reg);
|
||||
} else if ((offset)<0) {
|
||||
STR_index(base, Scratch, reg);
|
||||
NEG(Scratch);
|
||||
if (offset < -255) {
|
||||
NanoAssert(offset >= -1020);
|
||||
SHLi(Scratch, 2);
|
||||
MOVi(Scratch, -off);
|
||||
}
|
||||
else {
|
||||
MOVi(Scratch, -offset);
|
||||
}
|
||||
} else {
|
||||
underrunProtect(6);
|
||||
if (off<32) {
|
||||
STR_m(base, offset, reg);
|
||||
}
|
||||
else {
|
||||
STR_index(base, Scratch, reg);
|
||||
if (offset > 255) {
|
||||
SHLi(Scratch, 2);
|
||||
MOVi(Scratch, off);
|
||||
}
|
||||
else {
|
||||
MOVi(Scratch, offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void Assembler::ADDi8(Register r, int32_t i)
|
||||
{
|
||||
underrunProtect(2);
|
||||
NanoAssert(isU8(i));
|
||||
*(--_nIns) = (NIns)(0x3000 | r<<8 | i);
|
||||
asm_output2("add %s,#%d", gpn(r), i);
|
||||
}
|
||||
|
||||
void Assembler::ADDi(Register r, int32_t i)
|
||||
{
|
||||
if (i < 0 && i != 0x80000000) {
|
||||
SUBi(r, -i);
|
||||
}
|
||||
else if (r == SP) {
|
||||
NanoAssert((i&3)==0 && i >= 0 && i < (1<<9));
|
||||
underrunProtect(2);
|
||||
*(--_nIns) = (NIns)(0xB000 | i>>2);
|
||||
asm_output2("add %s,#%d", gpn(SP), i);
|
||||
}
|
||||
else if (isU8(i)) {
|
||||
ADDi8(r,i);
|
||||
}
|
||||
else if (i >= 0 && i <= (255+255)) {
|
||||
ADDi8(r,i-255);
|
||||
ADDi8(r,255);
|
||||
}
|
||||
else {
|
||||
ADD(r, Scratch);
|
||||
LDi(Scratch, i);
|
||||
}
|
||||
}
|
||||
|
||||
void Assembler::SUBi8(Register r, int32_t i)
|
||||
{
|
||||
underrunProtect(2);
|
||||
NanoAssert(isU8(i));
|
||||
*(--_nIns) = (NIns)(0x3800 | r<<8 | i);
|
||||
asm_output2("sub %s,#%d", gpn(r), i);
|
||||
}
|
||||
|
||||
void Assembler::SUBi(Register r, int32_t i)
|
||||
{
|
||||
if (i < 0 && i != 0x80000000) {
|
||||
ADDi(r, -i);
|
||||
}
|
||||
else if (r == SP) {
|
||||
NanoAssert((i&3)==0 && i >= 0 && i < (1<<9));
|
||||
underrunProtect(2);
|
||||
*(--_nIns) = (NIns)(0xB080 | i>>2);
|
||||
asm_output2("sub %s,#%d", gpn(SP), i);
|
||||
}
|
||||
else if (isU8(i)) {
|
||||
SUBi8(r,i);
|
||||
}
|
||||
else if (i >= 0 && i <= (255+255)) {
|
||||
SUBi8(r,i-255);
|
||||
SUBi8(r,255);
|
||||
}
|
||||
else {
|
||||
SUB(r, Scratch);
|
||||
LDi(Scratch, i);
|
||||
}
|
||||
}
|
||||
|
||||
void Assembler::CALL(intptr_t addr, const char* nm)
|
||||
{
|
||||
(void)nm;
|
||||
if (isB22((NIns*)addr, _nIns)) {
|
||||
int offset = int(addr)-int(_nIns-2+2);
|
||||
*(--_nIns) = (NIns)(0xF800 | ((offset>>1)&0x7FF) );
|
||||
*(--_nIns) = (NIns)(0xF000 | ((offset>>12)&0x7FF) );
|
||||
asm_output2("call %08X:%s",(addr),(nm));
|
||||
}
|
||||
else
|
||||
{
|
||||
underrunProtect(2*(10));
|
||||
|
||||
if ( (((int(_nIns))&0xFFFF)%4) != 0)
|
||||
*(--_nIns) = (NIns)0;
|
||||
|
||||
*(--_nIns) = (NIns)(0xF800 | (((-14)&0xFFF)>>1) );
|
||||
*(--_nIns) = (NIns)(0xF000 | (((-14)>>12)&0x7FF) );
|
||||
|
||||
*(--_nIns) = (NIns)(0x4600 | (1<<7) | (Scratch<<3) | (IP&7));
|
||||
*(--_nIns) = (NIns)0;
|
||||
*(--_nIns) = (short)((addr) >> 16);
|
||||
*(--_nIns) = (short)((addr) & 0xFFFF);
|
||||
*(--_nIns) = (NIns)(0x4700 | (IP<<3));
|
||||
*(--_nIns) = (NIns)(0xE000 | (4>>1));
|
||||
*(--_nIns) = (NIns)(0x4800 | (Scratch<<8) | (1));
|
||||
asm_output2("call %08X:%s",(addr),(nm));
|
||||
}
|
||||
}
|
||||
|
||||
#else // ARM_JIT
|
||||
void Assembler::underrunProtect(int bytes)
|
||||
{
|
||||
intptr_t u = (bytes) + 4;
|
||||
if ( (samepage(_nIns,_nSlot) && (((intptr_t)_nIns-u) <= intptr_t(_nSlot+1))) ||
|
||||
(!samepage((intptr_t)_nIns-u,_nIns)) )
|
||||
{
|
||||
NIns* target = _nIns;
|
||||
_nIns = pageAlloc(_inExit);
|
||||
JMP_nochk(target);
|
||||
_nSlot = pageTop(_nIns);
|
||||
}
|
||||
}
|
||||
|
||||
bool isB24(NIns *target, NIns *cur)
|
||||
{
|
||||
int offset = int(target)-int(cur-2+2);
|
||||
return (-(1<<24) <= offset && offset < (1<<24));
|
||||
}
|
||||
|
||||
void Assembler::CALL(intptr_t addr, const char* nm)
|
||||
{
|
||||
(void)nm;
|
||||
if (isB24((NIns*)addr,_nIns))
|
||||
{
|
||||
// we can do this with a single BL call
|
||||
underrunProtect(4);
|
||||
|
||||
BL(addr);
|
||||
asm_output2("call %08X:%s",(addr),(nm));
|
||||
}
|
||||
else
|
||||
{
|
||||
underrunProtect(16);
|
||||
*(--_nIns) = (NIns)((addr));
|
||||
*(--_nIns) = (NIns)( COND_AL | (0x9<<21) | (0xFFF<<8) | (1<<4) | (IP) );
|
||||
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | (PC<<16) | (LR<<12) | (4) );
|
||||
*(--_nIns) = (NIns)( COND_AL | (0x59<<20) | (PC<<16) | (IP<<12) | (4));
|
||||
asm_output2("call %08X:%s",(addr),(nm));
|
||||
}
|
||||
}
|
||||
|
||||
#endif // NJ_THUMB_JIT
|
||||
|
||||
|
||||
void Assembler::LD32_nochk(Register r, int32_t imm)
|
||||
{
|
||||
#ifdef NJ_THUMB_JIT
|
||||
|
||||
// Can we reach the current slot/pool?
|
||||
int offset = (int)(_nSlot) - (int)(_nIns);
|
||||
if ((offset>=NJ_MAX_CPOOL_OFFSET || offset<0) ||
|
||||
(_nSlot < _nPool))
|
||||
{
|
||||
// cant reach, or no room
|
||||
// need a new pool
|
||||
|
||||
// Make sure we have space for a pool and the LDR
|
||||
underrunProtect(sizeof(int32_t)*NJ_CPOOL_SIZE+1);
|
||||
|
||||
NIns* skip = _nIns;
|
||||
|
||||
_nPool = (int*)(((int)_nIns - (sizeof(int32_t)*NJ_CPOOL_SIZE)) &~3);
|
||||
_nSlot = _nPool + (NJ_CPOOL_SIZE-1);
|
||||
_nIns = (NIns*)_nPool;
|
||||
|
||||
// jump over the pool
|
||||
B(skip);
|
||||
//*(--_nIns) = (NIns)( COND_AL | (0x5<<25) | (NJ_CPOOL_SIZE-1) );
|
||||
}
|
||||
|
||||
*(_nSlot--) = (int)imm;
|
||||
|
||||
NIns *data = (NIns*)(_nSlot+1);;
|
||||
|
||||
int data_off = int(data) - (int(_nIns+1)&~3);
|
||||
*(--_nIns) = (NIns)(0x4800 | r<<8 | data_off>>2);
|
||||
asm_output3("ldr %s,%d(PC) [%X]",gpn(r),data_off,(int)data);
|
||||
|
||||
|
||||
#else
|
||||
|
||||
// We can always reach the const pool, since it's on the same page (<4096)
|
||||
|
||||
if (!_nSlot)
|
||||
_nSlot = pageTop(_nIns);
|
||||
|
||||
if ( (_nSlot+1) >= (_nIns-1) )
|
||||
{
|
||||
// This would overrun the code, so we need a new page
|
||||
// and a jump to that page
|
||||
|
||||
NIns* target = _nIns;
|
||||
_nIns = pageAlloc(_inExit);
|
||||
JMP_nochk(target);
|
||||
|
||||
// reset the slot
|
||||
_nSlot = pageTop(_nIns);
|
||||
}
|
||||
|
||||
*(++_nSlot) = (int)imm;
|
||||
|
||||
int offset = (int)(_nSlot) - (int)(_nIns+1);
|
||||
|
||||
*(--_nIns) = (NIns)( COND_AL | (0x51<<20) | (PC<<16) | ((r)<<12) | -(offset));
|
||||
asm_output2("ld %s,%d",gpn(r),imm);
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
}
|
||||
#endif /* FEATURE_NANOJIT */
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user