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Bug 1013996 - IonMonkey ARM: Simulator alignment checks and irregexp aligned access support. r=lth
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@ -1320,7 +1320,9 @@ NativeRegExpMacroAssembler::CheckSpecialCharacterClass(char16_t type, Label* on_
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bool
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NativeRegExpMacroAssembler::CanReadUnaligned()
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{
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#if defined(JS_CODEGEN_ARM) || defined(JS_CODEGEN_MIPS)
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#if defined(JS_CODEGEN_ARM)
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return !jit::HasAlignmentFault();
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#elif defined(JS_CODEGEN_MIPS)
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return false;
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#else
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return true;
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@ -38,20 +38,6 @@
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# endif
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#endif
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// Not part of the HWCAP flag, but we need to know these and these bits are not used.
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// A bit to flag the use of the ARMv7 arch, otherwise ARMv6.
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#define HWCAP_ARMv7 (1 << 28)
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// A bit to flag the use of the hardfp ABI.
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#define HWCAP_USE_HARDFP_ABI (1 << 27)
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// A bit to flag when alignment faults are enabled and signal.
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#define HWCAP_ALIGNMENT_FAULT (1 << 26)
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// A bit to flag when the flags are uninitialized, so they can be atomically set.
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#define HWCAP_UNINITIALIZED (1 << 25)
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namespace js {
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namespace jit {
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@ -142,7 +128,7 @@ CanonicalizeARMHwCapFlags(uint32_t flags)
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// The override flags parsed from the ARMHWCAP environment variable or from the
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// --arm-hwcap js shell argument.
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volatile static uint32_t armHwCapFlags = HWCAP_UNINITIALIZED;
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volatile uint32_t armHwCapFlags = HWCAP_UNINITIALIZED;
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bool
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ParseARMHwCapFlags(const char *armHwCap)
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@ -317,14 +303,6 @@ bool HasIDIV()
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return armHwCapFlags & HWCAP_IDIVA;
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}
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// Returns true when cpu alignment faults are enabled and signaled, and thus we
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// should ensure loads and stores are aligned.
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bool HasAlignmentFault()
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{
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MOZ_ASSERT(armHwCapFlags != HWCAP_UNINITIALIZED);
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return armHwCapFlags & HWCAP_ALIGNMENT_FAULT;
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}
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// This is defined in the header and inlined when not using the simulator.
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#if defined(JS_ARM_SIMULATOR)
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bool UseHardFpABI()
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@ -521,7 +521,31 @@ bool HasVFPv3();
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bool HasVFP();
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bool Has32DP();
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bool HasIDIV();
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bool HasAlignmentFault();
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extern volatile uint32_t armHwCapFlags;
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// Not part of the HWCAP flag, but we need to know these and these bits are not
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// used. Define these here so that their use can be inlined by the simulator.
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// A bit to flag when the flags are uninitialized, so they can be atomically set.
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#define HWCAP_UNINITIALIZED (1 << 25)
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// A bit to flag when alignment faults are enabled and signal.
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#define HWCAP_ALIGNMENT_FAULT (1 << 26)
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// A bit to flag the use of the hardfp ABI.
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#define HWCAP_USE_HARDFP_ABI (1 << 27)
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// A bit to flag the use of the ARMv7 arch, otherwise ARMv6.
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#define HWCAP_ARMv7 (1 << 28)
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// Returns true when cpu alignment faults are enabled and signaled, and thus we
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// should ensure loads and stores are aligned.
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inline bool HasAlignmentFault()
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{
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MOZ_ASSERT(armHwCapFlags != HWCAP_UNINITIALIZED);
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return armHwCapFlags & HWCAP_ALIGNMENT_FAULT;
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}
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// Arm/D32 has double registers that can NOT be treated as float32 and this
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// requires some dances in lowering.
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@ -1493,8 +1493,13 @@ Simulator::readW(int32_t addr, SimInstruction *instr)
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{
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// The regexp engine emits unaligned loads, so we don't check for them here
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// like most of the other methods do.
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intptr_t *ptr = reinterpret_cast<intptr_t*>(addr);
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return *ptr;
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if ((addr & 3) == 0 || !HasAlignmentFault()) {
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intptr_t *ptr = reinterpret_cast<intptr_t*>(addr);
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return *ptr;
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} else {
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printf("Unaligned write at 0x%08x, pc=%p\n", addr, instr);
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MOZ_CRASH();
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}
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}
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void
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@ -1514,8 +1519,13 @@ Simulator::readHU(int32_t addr, SimInstruction *instr)
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{
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// The regexp engine emits unaligned loads, so we don't check for them here
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// like most of the other methods do.
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uint16_t *ptr = reinterpret_cast<uint16_t*>(addr);
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return *ptr;
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if ((addr & 1) == 0 || !HasAlignmentFault()) {
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uint16_t *ptr = reinterpret_cast<uint16_t*>(addr);
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return *ptr;
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}
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printf("Unaligned unsigned halfword read at 0x%08x, pc=%p\n", addr, instr);
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MOZ_CRASH();
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return 0;
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}
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int16_t
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