diff --git a/js/src/asmjs/AsmJSValidate.cpp b/js/src/asmjs/AsmJSValidate.cpp index 0cd84683582..28d79f07cbc 100644 --- a/js/src/asmjs/AsmJSValidate.cpp +++ b/js/src/asmjs/AsmJSValidate.cpp @@ -7165,13 +7165,13 @@ GenerateEntry(ModuleValidator& m, unsigned exportIndex) masm.storeFloat32(ScratchFloat32Reg, Address(masm.getStackPointer(), iter->offsetFromArgBase())); break; case MIRType_Int32x4: - masm.loadUnalignedInt32x4(src, ScratchSimd128Reg); - masm.storeAlignedInt32x4(ScratchSimd128Reg, + masm.loadUnalignedInt32x4(src, ScratchSimdReg); + masm.storeAlignedInt32x4(ScratchSimdReg, Address(masm.getStackPointer(), iter->offsetFromArgBase())); break; case MIRType_Float32x4: - masm.loadUnalignedFloat32x4(src, ScratchSimd128Reg); - masm.storeAlignedFloat32x4(ScratchSimd128Reg, + masm.loadUnalignedFloat32x4(src, ScratchSimdReg); + masm.storeAlignedFloat32x4(ScratchSimdReg, Address(masm.getStackPointer(), iter->offsetFromArgBase())); break; default: @@ -7211,11 +7211,11 @@ GenerateEntry(ModuleValidator& m, unsigned exportIndex) break; case RetType::Int32x4: // We don't have control on argv alignment, do an unaligned access. - masm.storeUnalignedInt32x4(ReturnSimd128Reg, Address(argv, 0)); + masm.storeUnalignedInt32x4(ReturnInt32x4Reg, Address(argv, 0)); break; case RetType::Float32x4: // We don't have control on argv alignment, do an unaligned access. - masm.storeUnalignedFloat32x4(ReturnSimd128Reg, Address(argv, 0)); + masm.storeUnalignedFloat32x4(ReturnFloat32x4Reg, Address(argv, 0)); break; } diff --git a/js/src/jit/JitFrames.cpp b/js/src/jit/JitFrames.cpp index 1446357405d..a7edc38c3a6 100644 --- a/js/src/jit/JitFrames.cpp +++ b/js/src/jit/JitFrames.cpp @@ -2602,7 +2602,8 @@ MachineState::FromBailout(RegisterDump::GPRArray& regs, RegisterDump::FPUArray& for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) { machine.setRegisterLocation(FloatRegister(i, FloatRegisters::Single), &fpregs[i]); machine.setRegisterLocation(FloatRegister(i, FloatRegisters::Double), &fpregs[i]); - machine.setRegisterLocation(FloatRegister(i, FloatRegisters::Simd128), &fpregs[i]); + machine.setRegisterLocation(FloatRegister(i, FloatRegisters::Int32x4), &fpregs[i]); + machine.setRegisterLocation(FloatRegister(i, FloatRegisters::Float32x4), &fpregs[i]); } #elif defined(JS_CODEGEN_ARM64) for (unsigned i = 0; i < FloatRegisters::TotalPhys; i++) { diff --git a/js/src/jit/LIR.h b/js/src/jit/LIR.h index b4ff10a4c62..83d663a4eb4 100644 --- a/js/src/jit/LIR.h +++ b/js/src/jit/LIR.h @@ -484,8 +484,10 @@ class LDefinition return r.fpu().isSingle(); if (type() == DOUBLE) return r.fpu().isDouble(); - if (isSimdType()) - return r.fpu().isSimd128(); + if (type() == INT32X4) + return r.fpu().isInt32x4(); + if (type() == FLOAT32X4) + return r.fpu().isFloat32x4(); MOZ_CRASH("Unexpected MDefinition type"); } return !isFloatReg() && !r.isFloat(); diff --git a/js/src/jit/Lowering.cpp b/js/src/jit/Lowering.cpp index ed50b77a7de..66f9604afec 100644 --- a/js/src/jit/Lowering.cpp +++ b/js/src/jit/Lowering.cpp @@ -3846,8 +3846,10 @@ LIRGenerator::visitAsmJSReturn(MAsmJSReturn* ins) lir->setOperand(0, useFixed(rval, ReturnFloat32Reg)); else if (rval->type() == MIRType_Double) lir->setOperand(0, useFixed(rval, ReturnDoubleReg)); - else if (IsSimdType(rval->type())) - lir->setOperand(0, useFixed(rval, ReturnSimd128Reg)); + else if (rval->type() == MIRType_Int32x4) + lir->setOperand(0, useFixed(rval, ReturnInt32x4Reg)); + else if (rval->type() == MIRType_Float32x4) + lir->setOperand(0, useFixed(rval, ReturnFloat32x4Reg)); else if (rval->type() == MIRType_Int32) lir->setOperand(0, useFixed(rval, ReturnReg)); else diff --git a/js/src/jit/Recover.cpp b/js/src/jit/Recover.cpp index fae79ea90d4..7142323ba64 100644 --- a/js/src/jit/Recover.cpp +++ b/js/src/jit/Recover.cpp @@ -1341,12 +1341,12 @@ RSimdBox::recover(JSContext* cx, SnapshotIterator& iter) const switch (SimdTypeDescr::Type(type_)) { case SimdTypeDescr::Int32x4: MOZ_ASSERT_IF(a.mode() == RValueAllocation::ANY_FLOAT_REG, - a.fpuReg().isSimd128()); + a.fpuReg().isInt32x4()); resultObject = js::CreateSimd(cx, (const Int32x4::Elem*) raw); break; case SimdTypeDescr::Float32x4: MOZ_ASSERT_IF(a.mode() == RValueAllocation::ANY_FLOAT_REG, - a.fpuReg().isSimd128()); + a.fpuReg().isFloat32x4()); resultObject = js::CreateSimd(cx, (const Float32x4::Elem*) raw); break; case SimdTypeDescr::Float64x2: diff --git a/js/src/jit/arm/Architecture-arm.h b/js/src/jit/arm/Architecture-arm.h index 12b0a1242a0..1318880f665 100644 --- a/js/src/jit/arm/Architecture-arm.h +++ b/js/src/jit/arm/Architecture-arm.h @@ -391,7 +391,8 @@ class VFPRegister bool isSingle() const { return kind == Single; } bool isDouble() const { return kind == Double; } - bool isSimd128() const { return false; } + bool isInt32x4() const { return false; } + bool isFloat32x4() const { return false; } bool isFloat() const { return (kind == Double) || (kind == Single); } bool isInt() const { return (kind == UInt) || (kind == Int); } bool isSInt() const { return kind == Int; } @@ -408,7 +409,8 @@ class VFPRegister VFPRegister asSingle() const { return singleOverlay(); } VFPRegister asDouble() const { return doubleOverlay(); } - VFPRegister asSimd128() const { MOZ_CRASH("NYI"); } + VFPRegister asInt32x4() const { MOZ_CRASH("NYI"); } + VFPRegister asFloat32x4() const { MOZ_CRASH("NYI"); } struct VFPRegIndexSplit; VFPRegIndexSplit encode(); diff --git a/js/src/jit/arm/Assembler-arm.h b/js/src/jit/arm/Assembler-arm.h index a348846f28a..30f8bb07b87 100644 --- a/js/src/jit/arm/Assembler-arm.h +++ b/js/src/jit/arm/Assembler-arm.h @@ -120,10 +120,11 @@ static MOZ_CONSTEXPR_VAR Register FramePointer = InvalidReg; static MOZ_CONSTEXPR_VAR Register ReturnReg = r0; static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32Reg = { FloatRegisters::d0, VFPRegister::Single }; static MOZ_CONSTEXPR_VAR FloatRegister ReturnDoubleReg = { FloatRegisters::d0, VFPRegister::Double}; -static MOZ_CONSTEXPR_VAR FloatRegister ReturnSimd128Reg = InvalidFloatReg; +static MOZ_CONSTEXPR_VAR FloatRegister ReturnInt32x4Reg = InvalidFloatReg; +static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32x4Reg = InvalidFloatReg; static MOZ_CONSTEXPR_VAR FloatRegister ScratchFloat32Reg = { FloatRegisters::d30, VFPRegister::Single }; static MOZ_CONSTEXPR_VAR FloatRegister ScratchDoubleReg = { FloatRegisters::d15, VFPRegister::Double }; -static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimd128Reg = InvalidFloatReg; +static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimdReg = InvalidFloatReg; static MOZ_CONSTEXPR_VAR FloatRegister ScratchUIntReg = { FloatRegisters::d15, VFPRegister::UInt }; static MOZ_CONSTEXPR_VAR FloatRegister ScratchIntReg = { FloatRegisters::d15, VFPRegister::Int }; diff --git a/js/src/jit/arm64/Architecture-arm64.h b/js/src/jit/arm64/Architecture-arm64.h index b486dc66c8e..0c92cfe81be 100644 --- a/js/src/jit/arm64/Architecture-arm64.h +++ b/js/src/jit/arm64/Architecture-arm64.h @@ -411,7 +411,10 @@ struct FloatRegister bool isDouble() const { return k_ == FloatRegisters::Double; } - bool isSimd128() const { + bool isInt32x4() const { + return false; + } + bool isFloat32x4() const { return false; } diff --git a/js/src/jit/arm64/Assembler-arm64.h b/js/src/jit/arm64/Assembler-arm64.h index e53b74df6a0..529efb5146e 100644 --- a/js/src/jit/arm64/Assembler-arm64.h +++ b/js/src/jit/arm64/Assembler-arm64.h @@ -64,8 +64,8 @@ static constexpr Register ZeroRegister = { Registers::sp }; static constexpr ARMRegister ZeroRegister64 = { Registers::sp, 64 }; static constexpr ARMRegister ZeroRegister32 = { Registers::sp, 32 }; -static constexpr FloatRegister ReturnSimd128Reg = InvalidFloatReg; -static constexpr FloatRegister ScratchSimd128Reg = InvalidFloatReg; +static constexpr FloatRegister ReturnSimdReg = InvalidFloatReg; +static constexpr FloatRegister ScratchSimdReg = InvalidFloatReg; // StackPointer is intentionally undefined on ARM64 to prevent misuse: // using sp as a base register is only valid if sp % 16 == 0. diff --git a/js/src/jit/mips-shared/Architecture-mips-shared.h b/js/src/jit/mips-shared/Architecture-mips-shared.h index ebb12768688..4b613dd2137 100644 --- a/js/src/jit/mips-shared/Architecture-mips-shared.h +++ b/js/src/jit/mips-shared/Architecture-mips-shared.h @@ -289,7 +289,8 @@ class TypedRegisterSet; class FloatRegisterMIPSShared { public: - bool isSimd128() const { return false; } + bool isInt32x4() const { return false; } + bool isFloat32x4() const { return false; } typedef FloatRegistersMIPSShared::SetType SetType; diff --git a/js/src/jit/mips-shared/Assembler-mips-shared.h b/js/src/jit/mips-shared/Assembler-mips-shared.h index 843589d28dd..e8447908c00 100644 --- a/js/src/jit/mips-shared/Assembler-mips-shared.h +++ b/js/src/jit/mips-shared/Assembler-mips-shared.h @@ -104,8 +104,9 @@ static MOZ_CONSTEXPR_VAR FloatRegister InvalidFloatReg; static MOZ_CONSTEXPR_VAR Register StackPointer = sp; static MOZ_CONSTEXPR_VAR Register FramePointer = InvalidReg; static MOZ_CONSTEXPR_VAR Register ReturnReg = v0; -static MOZ_CONSTEXPR_VAR FloatRegister ReturnSimd128Reg = InvalidFloatReg; -static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimd128Reg = InvalidFloatReg; +static MOZ_CONSTEXPR_VAR FloatRegister ReturnInt32x4Reg = InvalidFloatReg; +static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32x4Reg = InvalidFloatReg; +static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimdReg = InvalidFloatReg; // A bias applied to the GlobalReg to allow the use of instructions with small // negative immediate offsets which doubles the range of global data that can be diff --git a/js/src/jit/none/MacroAssembler-none.h b/js/src/jit/none/MacroAssembler-none.h index 2c9c6e75947..95dba992643 100644 --- a/js/src/jit/none/MacroAssembler-none.h +++ b/js/src/jit/none/MacroAssembler-none.h @@ -24,7 +24,7 @@ static MOZ_CONSTEXPR_VAR FloatRegister ReturnInt32x4Reg = { FloatRegisters::inva static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32x4Reg = { FloatRegisters::invalid_reg }; static MOZ_CONSTEXPR_VAR FloatRegister ScratchFloat32Reg = { FloatRegisters::invalid_reg }; static MOZ_CONSTEXPR_VAR FloatRegister ScratchDoubleReg = { FloatRegisters::invalid_reg }; -static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimd128Reg = { FloatRegisters::invalid_reg }; +static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimdReg = { FloatRegisters::invalid_reg }; static MOZ_CONSTEXPR_VAR FloatRegister InvalidFloatReg = { FloatRegisters::invalid_reg }; static MOZ_CONSTEXPR_VAR Register OsrFrameReg = { Registers::invalid_reg }; diff --git a/js/src/jit/shared/CodeGenerator-shared.cpp b/js/src/jit/shared/CodeGenerator-shared.cpp index 3ed51e91f37..7e4de5a3aa5 100644 --- a/js/src/jit/shared/CodeGenerator-shared.cpp +++ b/js/src/jit/shared/CodeGenerator-shared.cpp @@ -1157,7 +1157,9 @@ class StoreOp else if (reg.isSingle()) masm.storeFloat32(reg, dump); #if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64) - else if (reg.isSimd128()) + else if (reg.isInt32x4()) + masm.storeUnalignedInt32x4(reg, dump); + else if (reg.isFloat32x4()) masm.storeUnalignedFloat32x4(reg, dump); #endif else diff --git a/js/src/jit/shared/Lowering-shared-inl.h b/js/src/jit/shared/Lowering-shared-inl.h index 42f69b8d1f9..89b6659ca0d 100644 --- a/js/src/jit/shared/Lowering-shared-inl.h +++ b/js/src/jit/shared/Lowering-shared-inl.h @@ -160,10 +160,10 @@ LIRGeneratorShared::defineReturn(LInstruction* lir, MDefinition* mir) lir->setDef(0, LDefinition(vreg, LDefinition::DOUBLE, LFloatReg(ReturnDoubleReg))); break; case MIRType_Int32x4: - lir->setDef(0, LDefinition(vreg, LDefinition::INT32X4, LFloatReg(ReturnSimd128Reg))); + lir->setDef(0, LDefinition(vreg, LDefinition::INT32X4, LFloatReg(ReturnInt32x4Reg))); break; case MIRType_Float32x4: - lir->setDef(0, LDefinition(vreg, LDefinition::FLOAT32X4, LFloatReg(ReturnSimd128Reg))); + lir->setDef(0, LDefinition(vreg, LDefinition::FLOAT32X4, LFloatReg(ReturnFloat32x4Reg))); break; default: LDefinition::Type type = LDefinition::TypeFrom(mir->type()); diff --git a/js/src/jit/x64/Assembler-x64.cpp b/js/src/jit/x64/Assembler-x64.cpp index 6d746be88cd..419a1091409 100644 --- a/js/src/jit/x64/Assembler-x64.cpp +++ b/js/src/jit/x64/Assembler-x64.cpp @@ -101,7 +101,10 @@ ABIArgGenerator::next(MIRType type) stackOffset_ += Simd128DataSize; break; } - current_ = ABIArg(FloatArgRegs[floatRegIndex_++].asSimd128()); + if (type == MIRType_Int32x4) + current_ = ABIArg(FloatArgRegs[floatRegIndex_++].asInt32x4()); + else + current_ = ABIArg(FloatArgRegs[floatRegIndex_++].asFloat32x4()); break; default: MOZ_CRASH("Unexpected argument type"); diff --git a/js/src/jit/x64/Assembler-x64.h b/js/src/jit/x64/Assembler-x64.h index 4247c5d01d0..b0fbb308217 100644 --- a/js/src/jit/x64/Assembler-x64.h +++ b/js/src/jit/x64/Assembler-x64.h @@ -85,10 +85,11 @@ static MOZ_CONSTEXPR_VAR Register ReturnReg = rax; static MOZ_CONSTEXPR_VAR Register HeapReg = r15; static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Single); static MOZ_CONSTEXPR_VAR FloatRegister ReturnDoubleReg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Double); -static MOZ_CONSTEXPR_VAR FloatRegister ReturnSimd128Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Simd128); +static MOZ_CONSTEXPR_VAR FloatRegister ReturnInt32x4Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Int32x4); +static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32x4Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Float32x4); static MOZ_CONSTEXPR_VAR FloatRegister ScratchFloat32Reg = FloatRegister(X86Encoding::xmm15, FloatRegisters::Single); static MOZ_CONSTEXPR_VAR FloatRegister ScratchDoubleReg = FloatRegister(X86Encoding::xmm15, FloatRegisters::Double); -static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimd128Reg = xmm15; +static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimdReg = xmm15; // Avoid rbp, which is the FramePointer, which is unavailable in some modes. static MOZ_CONSTEXPR_VAR Register ArgumentsRectifierReg = r8; diff --git a/js/src/jit/x64/CodeGenerator-x64.cpp b/js/src/jit/x64/CodeGenerator-x64.cpp index 0c414205c96..eeb74d91fc8 100644 --- a/js/src/jit/x64/CodeGenerator-x64.cpp +++ b/js/src/jit/x64/CodeGenerator-x64.cpp @@ -336,15 +336,14 @@ CodeGeneratorX64::emitSimdLoad(LAsmJSLoadHeap* ins) // This is still in bounds, as we've checked with a manual bounds check // or we had enough space for sure when removing the bounds check. before = after; - loadSimd(type, 1, srcAddrZ, ScratchSimd128Reg); + loadSimd(type, 1, srcAddrZ, ScratchSimdReg); after = masm.size(); - verifyHeapAccessDisassembly(before, after, /*isLoad=*/true, type, 1, srcAddrZ, - LFloatReg(ScratchSimd128Reg)); + verifyHeapAccessDisassembly(before, after, /*isLoad=*/true, type, 1, srcAddrZ, LFloatReg(ScratchSimdReg)); masm.append(AsmJSHeapAccess(before, AsmJSHeapAccess::Throw, AsmJSHeapAccess::NoLengthCheck, 8)); // Move ZW atop XY - masm.vmovlhps(ScratchSimd128Reg, out, out); + masm.vmovlhps(ScratchSimdReg, out, out); } else { uint32_t before = masm.size(); loadSimd(type, numElems, srcAddr, out); @@ -484,12 +483,11 @@ CodeGeneratorX64::emitSimdStore(LAsmJSStoreHeap* ins) // store the Z first, and record its offset in the AsmJSHeapAccess so // that the signal handler knows to check the bounds of the full // access, rather than just the Z. - masm.vmovhlps(in, ScratchSimd128Reg, ScratchSimd128Reg); + masm.vmovhlps(in, ScratchSimdReg, ScratchSimdReg); uint32_t before = masm.size(); - storeSimd(type, 1, ScratchSimd128Reg, dstAddrZ); + storeSimd(type, 1, ScratchSimdReg, dstAddrZ); uint32_t after = masm.size(); - verifyHeapAccessDisassembly(before, after, /*isLoad=*/false, type, 1, dstAddrZ, - LFloatReg(ScratchSimd128Reg)); + verifyHeapAccessDisassembly(before, after, /*isLoad=*/false, type, 1, dstAddrZ, LFloatReg(ScratchSimdReg)); masm.append(AsmJSHeapAccess(before, AsmJSHeapAccess::Throw, maybeCmpOffset, 8)); // Store XY diff --git a/js/src/jit/x86-shared/Architecture-x86-shared.cpp b/js/src/jit/x86-shared/Architecture-x86-shared.cpp index 5069d8ac989..5386420b0fd 100644 --- a/js/src/jit/x86-shared/Architecture-x86-shared.cpp +++ b/js/src/jit/x86-shared/Architecture-x86-shared.cpp @@ -63,8 +63,10 @@ uint32_t js::jit::FloatRegister::GetPushSizeInBytes(const FloatRegisterSet& s) { SetType all = s.bits(); - SetType set128b = - (all >> (uint32_t(Codes::Simd128) * Codes::TotalPhys)) & Codes::AllPhysMask; + SetType float32x4Set = + (all >> (uint32_t(Codes::Float32x4) * Codes::TotalPhys)) & Codes::AllPhysMask; + SetType int32x4Set = + (all >> (uint32_t(Codes::Int32x4) * Codes::TotalPhys)) & Codes::AllPhysMask; SetType doubleSet = (all >> (uint32_t(Codes::Double) * Codes::TotalPhys)) & Codes::AllPhysMask; SetType singleSet = @@ -73,6 +75,7 @@ js::jit::FloatRegister::GetPushSizeInBytes(const FloatRegisterSet& s) // PushRegsInMask pushes the largest register first, and thus avoids pushing // aliased registers. So we have to filter out the physical registers which // are already pushed as part of larger registers. + SetType set128b = int32x4Set | float32x4Set; SetType set64b = doubleSet & ~set128b; SetType set32b = singleSet & ~set64b & ~set128b; diff --git a/js/src/jit/x86-shared/Architecture-x86-shared.h b/js/src/jit/x86-shared/Architecture-x86-shared.h index 89e82f4cbcb..1d9966e1a30 100644 --- a/js/src/jit/x86-shared/Architecture-x86-shared.h +++ b/js/src/jit/x86-shared/Architecture-x86-shared.h @@ -193,9 +193,10 @@ class FloatRegisters { typedef X86Encoding::XMMRegisterID Encoding; enum ContentType { - Single, // 32-bit float. - Double, // 64-bit double. - Simd128, // 128-bit SIMD type (int32x4, bool16x8, etc). + Single, + Double, + Int32x4, + Float32x4, NumTypes }; @@ -243,9 +244,10 @@ class FloatRegisters { // the bits of the physical register mask. static const SetType SpreadSingle = SetType(1) << (uint32_t(Single) * TotalPhys); static const SetType SpreadDouble = SetType(1) << (uint32_t(Double) * TotalPhys); - static const SetType SpreadSimd128 = SetType(1) << (uint32_t(Simd128) * TotalPhys); + static const SetType SpreadInt32x4 = SetType(1) << (uint32_t(Int32x4) * TotalPhys); + static const SetType SpreadFloat32x4 = SetType(1) << (uint32_t(Float32x4) * TotalPhys); static const SetType SpreadScalar = SpreadSingle | SpreadDouble; - static const SetType SpreadVector = SpreadSimd128; + static const SetType SpreadVector = SpreadInt32x4 | SpreadFloat32x4; static const SetType Spread = SpreadScalar | SpreadVector; static const SetType AllPhysMask = ((1 << TotalPhys) - 1); @@ -356,12 +358,14 @@ struct FloatRegister { bool isSingle() const { MOZ_ASSERT(!isInvalid()); return type_ == Codes::Single; } bool isDouble() const { MOZ_ASSERT(!isInvalid()); return type_ == Codes::Double; } - bool isSimd128() const { MOZ_ASSERT(!isInvalid()); return type_ == Codes::Simd128; } + bool isInt32x4() const { MOZ_ASSERT(!isInvalid()); return type_ == Codes::Int32x4; } + bool isFloat32x4() const { MOZ_ASSERT(!isInvalid()); return type_ == Codes::Float32x4; } bool isInvalid() const { return isInvalid_; } FloatRegister asSingle() const { MOZ_ASSERT(!isInvalid()); return FloatRegister(reg_, Codes::Single); } FloatRegister asDouble() const { MOZ_ASSERT(!isInvalid()); return FloatRegister(reg_, Codes::Double); } - FloatRegister asSimd128() const { MOZ_ASSERT(!isInvalid()); return FloatRegister(reg_, Codes::Simd128); } + FloatRegister asInt32x4() const { MOZ_ASSERT(!isInvalid()); return FloatRegister(reg_, Codes::Int32x4); } + FloatRegister asFloat32x4() const { MOZ_ASSERT(!isInvalid()); return FloatRegister(reg_, Codes::Float32x4); } uint32_t size() const { MOZ_ASSERT(!isInvalid()); @@ -369,7 +373,7 @@ struct FloatRegister { return sizeof(float); if (isDouble()) return sizeof(double); - MOZ_ASSERT(isSimd128()); + MOZ_ASSERT(isInt32x4() || isFloat32x4()); return 4 * sizeof(int32_t); } diff --git a/js/src/jit/x86-shared/Assembler-x86-shared.h b/js/src/jit/x86-shared/Assembler-x86-shared.h index 9a47b5ae90b..b2661f3167c 100644 --- a/js/src/jit/x86-shared/Assembler-x86-shared.h +++ b/js/src/jit/x86-shared/Assembler-x86-shared.h @@ -36,10 +36,10 @@ struct ScratchDoubleScope : public AutoFloatRegisterScope { } }; -struct ScratchSimd128Scope : public AutoFloatRegisterScope +struct ScratchSimdScope : public AutoFloatRegisterScope { - explicit ScratchSimd128Scope(MacroAssembler& masm) - : AutoFloatRegisterScope(masm, ScratchSimd128Reg) + explicit ScratchSimdScope(MacroAssembler& masm) + : AutoFloatRegisterScope(masm, ScratchSimdReg) { } }; @@ -2207,8 +2207,8 @@ class AssemblerX86Shared : public AssemblerShared if (src1.kind() == Operand::FPREG && dest.aliases(FloatRegister::FromCode(src1.fpu()))) { - vmovdqa(src1, ScratchSimd128Reg); - src1 = Operand(ScratchSimd128Reg); + vmovdqa(src1, ScratchSimdReg); + src1 = Operand(ScratchSimdReg); } vmovdqa(src0, dest); src0 = dest; diff --git a/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp b/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp index 2dc37b73fde..e8bdaac25e7 100644 --- a/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp +++ b/js/src/jit/x86-shared/CodeGenerator-x86-shared.cpp @@ -2251,7 +2251,7 @@ CodeGeneratorX86Shared::visitFloat32x4ToInt32x4(LFloat32x4ToInt32x4* ins) static const SimdConstant InvalidResult = SimdConstant::SplatX4(int32_t(-2147483648)); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadConstantInt32x4(InvalidResult, scratch); masm.packedEqualInt32x4(Operand(out), scratch); // TODO (bug 1156228): If we have SSE4.1, we can use PTEST here instead of @@ -2277,7 +2277,7 @@ CodeGeneratorX86Shared::visitOutOfLineSimdFloatToIntCheck(OutOfLineSimdFloatToIn FloatRegister input = ool->input(); Register temp = ool->temp(); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadConstantFloat32x4(Int32MinX4, scratch); masm.vcmpleps(Operand(input), scratch, scratch); masm.vmovmskps(scratch, temp); @@ -2404,7 +2404,7 @@ CodeGeneratorX86Shared::visitSimdExtractElementI(LSimdExtractElementI* ins) masm.vpextrd(lane, input, output); } else { uint32_t mask = MacroAssembler::ComputeShuffleMask(lane); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.shuffleInt32(mask, input, scratch); masm.moveLowInt32(scratch, output); } @@ -2769,7 +2769,7 @@ CodeGeneratorX86Shared::visitSimdShuffle(LSimdShuffle* ins) // TODO Here and below, symmetric case would be more handy to avoid a move, // but can't be reached because operands would get swapped (bug 1084404). if (ins->lanesMatch(2, 3, 6, 7)) { - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); if (AssemblerX86Shared::HasAVX()) { FloatRegister rhsCopy = masm.reusedInputAlignedFloat32x4(rhs, scratch); masm.vmovhlps(lhs, rhsCopy, out); @@ -2783,7 +2783,7 @@ CodeGeneratorX86Shared::visitSimdShuffle(LSimdShuffle* ins) if (ins->lanesMatch(0, 1, 4, 5)) { FloatRegister rhsCopy; - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); if (rhs.kind() == Operand::FPREG) { // No need to make an actual copy, since the operand is already // in a register, and it won't be clobbered by the vmovlhps. @@ -2803,7 +2803,7 @@ CodeGeneratorX86Shared::visitSimdShuffle(LSimdShuffle* ins) // TODO swapped case would be better (bug 1084404) if (ins->lanesMatch(4, 0, 5, 1)) { - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); if (AssemblerX86Shared::HasAVX()) { FloatRegister rhsCopy = masm.reusedInputAlignedFloat32x4(rhs, scratch); masm.vunpcklps(lhs, rhsCopy, out); @@ -2822,7 +2822,7 @@ CodeGeneratorX86Shared::visitSimdShuffle(LSimdShuffle* ins) // TODO swapped case would be better (bug 1084404) if (ins->lanesMatch(6, 2, 7, 3)) { - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); if (AssemblerX86Shared::HasAVX()) { FloatRegister rhsCopy = masm.reusedInputAlignedFloat32x4(rhs, scratch); masm.vunpckhps(lhs, rhsCopy, out); @@ -2883,7 +2883,7 @@ CodeGeneratorX86Shared::visitSimdBinaryCompIx4(LSimdBinaryCompIx4* ins) Operand rhs = ToOperand(ins->rhs()); MOZ_ASSERT(ToFloatRegister(ins->output()) == lhs); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); MSimdBinaryComp::Operation op = ins->operation(); switch (op) { @@ -2970,7 +2970,7 @@ CodeGeneratorX86Shared::visitSimdBinaryArithIx4(LSimdBinaryArithIx4* ins) Operand rhs = ToOperand(ins->rhs()); FloatRegister output = ToFloatRegister(ins->output()); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); MSimdBinaryArith::Operation op = ins->operation(); switch (op) { @@ -3026,7 +3026,7 @@ CodeGeneratorX86Shared::visitSimdBinaryArithFx4(LSimdBinaryArithFx4* ins) Operand rhs = ToOperand(ins->rhs()); FloatRegister output = ToFloatRegister(ins->output()); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); MSimdBinaryArith::Operation op = ins->operation(); switch (op) { @@ -3692,10 +3692,12 @@ CodeGeneratorX86Shared::setReturnDoubleRegs(LiveRegisterSet* regs) { MOZ_ASSERT(ReturnFloat32Reg.encoding() == X86Encoding::xmm0); MOZ_ASSERT(ReturnDoubleReg.encoding() == X86Encoding::xmm0); - MOZ_ASSERT(ReturnSimd128Reg.encoding() == X86Encoding::xmm0); + MOZ_ASSERT(ReturnInt32x4Reg.encoding() == X86Encoding::xmm0); + MOZ_ASSERT(ReturnFloat32x4Reg.encoding() == X86Encoding::xmm0); regs->add(ReturnFloat32Reg); regs->add(ReturnDoubleReg); - regs->add(ReturnSimd128Reg); + regs->add(ReturnInt32x4Reg); + regs->add(ReturnFloat32x4Reg); } } // namespace jit diff --git a/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp b/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp index c872d5b9d22..f053813fa59 100644 --- a/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp +++ b/js/src/jit/x86-shared/MacroAssembler-x86-shared.cpp @@ -400,7 +400,9 @@ MacroAssembler::PushRegsInMask(LiveRegisterSet set) storeDouble(reg, spillAddress); else if (reg.isSingle()) storeFloat32(reg, spillAddress); - else if (reg.isSimd128()) + else if (reg.isInt32x4()) + storeUnalignedInt32x4(reg, spillAddress); + else if (reg.isFloat32x4()) storeUnalignedFloat32x4(reg, spillAddress); else MOZ_CRASH("Unknown register type."); @@ -434,7 +436,9 @@ MacroAssembler::PopRegsInMaskIgnore(LiveRegisterSet set, LiveRegisterSet ignore) loadDouble(spillAddress, reg); else if (reg.isSingle()) loadFloat32(spillAddress, reg); - else if (reg.isSimd128()) + else if (reg.isInt32x4()) + loadUnalignedInt32x4(spillAddress, reg); + else if (reg.isFloat32x4()) loadUnalignedFloat32x4(spillAddress, reg); else MOZ_CRASH("Unknown register type."); diff --git a/js/src/jit/x86-shared/MacroAssembler-x86-shared.h b/js/src/jit/x86-shared/MacroAssembler-x86-shared.h index 3a0c576c496..6510f9fbb9a 100644 --- a/js/src/jit/x86-shared/MacroAssembler-x86-shared.h +++ b/js/src/jit/x86-shared/MacroAssembler-x86-shared.h @@ -1009,7 +1009,7 @@ class MacroAssemblerX86Shared : public Assembler BaseIndex srcZ(src); srcZ.offset += 2 * sizeof(int32_t); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovq(Operand(src), dest); vmovd(Operand(srcZ), scratch); vmovlhps(scratch, dest, dest); @@ -1018,7 +1018,7 @@ class MacroAssemblerX86Shared : public Assembler Address srcZ(src); srcZ.offset += 2 * sizeof(int32_t); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovq(Operand(src), dest); vmovd(Operand(srcZ), scratch); vmovlhps(scratch, dest, dest); @@ -1074,7 +1074,7 @@ class MacroAssemblerX86Shared : public Assembler Address destZ(dest); destZ.offset += 2 * sizeof(int32_t); vmovq(src, Operand(dest)); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovhlps(src, scratch, scratch); vmovd(scratch, Operand(destZ)); } @@ -1082,7 +1082,7 @@ class MacroAssemblerX86Shared : public Assembler BaseIndex destZ(dest); destZ.offset += 2 * sizeof(int32_t); vmovq(src, Operand(dest)); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovhlps(src, scratch, scratch); vmovd(scratch, Operand(destZ)); } @@ -1145,7 +1145,7 @@ class MacroAssemblerX86Shared : public Assembler Address srcZ(src); srcZ.offset += 2 * sizeof(float); vmovsd(src, dest); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovss(srcZ, scratch); vmovlhps(scratch, dest, dest); } @@ -1153,7 +1153,7 @@ class MacroAssemblerX86Shared : public Assembler BaseIndex srcZ(src); srcZ.offset += 2 * sizeof(float); vmovsd(src, dest); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovss(srcZ, scratch); vmovlhps(scratch, dest, dest); } @@ -1169,7 +1169,7 @@ class MacroAssemblerX86Shared : public Assembler Address destZ(dest); destZ.offset += 2 * sizeof(int32_t); storeDouble(src, dest); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovhlps(src, scratch, scratch); storeFloat32(scratch, destZ); } @@ -1177,7 +1177,7 @@ class MacroAssemblerX86Shared : public Assembler BaseIndex destZ(dest); destZ.offset += 2 * sizeof(int32_t); storeDouble(src, dest); - ScratchSimd128Scope scratch(asMasm()); + ScratchSimdScope scratch(asMasm()); vmovhlps(src, scratch, scratch); storeFloat32(scratch, destZ); } diff --git a/js/src/jit/x86-shared/MoveEmitter-x86-shared.cpp b/js/src/jit/x86-shared/MoveEmitter-x86-shared.cpp index c0714b2bad1..7408b2e8551 100644 --- a/js/src/jit/x86-shared/MoveEmitter-x86-shared.cpp +++ b/js/src/jit/x86-shared/MoveEmitter-x86-shared.cpp @@ -251,7 +251,7 @@ MoveEmitterX86::breakCycle(const MoveOperand& to, MoveOp::Type type) switch (type) { case MoveOp::INT32X4: if (to.isMemory()) { - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadAlignedInt32x4(toAddress(to), scratch); masm.storeAlignedInt32x4(scratch, cycleSlot()); } else { @@ -260,7 +260,7 @@ MoveEmitterX86::breakCycle(const MoveOperand& to, MoveOp::Type type) break; case MoveOp::FLOAT32X4: if (to.isMemory()) { - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadAlignedFloat32x4(toAddress(to), scratch); masm.storeAlignedFloat32x4(scratch, cycleSlot()); } else { @@ -318,7 +318,7 @@ MoveEmitterX86::completeCycle(const MoveOperand& to, MoveOp::Type type) MOZ_ASSERT(pushedAtCycle_ != -1); MOZ_ASSERT(pushedAtCycle_ - pushedAtStart_ >= Simd128DataSize); if (to.isMemory()) { - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadAlignedInt32x4(cycleSlot(), scratch); masm.storeAlignedInt32x4(scratch, toAddress(to)); } else { @@ -329,7 +329,7 @@ MoveEmitterX86::completeCycle(const MoveOperand& to, MoveOp::Type type) MOZ_ASSERT(pushedAtCycle_ != -1); MOZ_ASSERT(pushedAtCycle_ - pushedAtStart_ >= Simd128DataSize); if (to.isMemory()) { - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadAlignedFloat32x4(cycleSlot(), scratch); masm.storeAlignedFloat32x4(scratch, toAddress(to)); } else { @@ -492,8 +492,8 @@ MoveEmitterX86::emitDoubleMove(const MoveOperand& from, const MoveOperand& to) void MoveEmitterX86::emitInt32X4Move(const MoveOperand& from, const MoveOperand& to) { - MOZ_ASSERT_IF(from.isFloatReg(), from.floatReg().isSimd128()); - MOZ_ASSERT_IF(to.isFloatReg(), to.floatReg().isSimd128()); + MOZ_ASSERT_IF(from.isFloatReg(), from.floatReg().isInt32x4()); + MOZ_ASSERT_IF(to.isFloatReg(), to.floatReg().isInt32x4()); if (from.isFloatReg()) { if (to.isFloatReg()) @@ -505,7 +505,7 @@ MoveEmitterX86::emitInt32X4Move(const MoveOperand& from, const MoveOperand& to) } else { // Memory to memory move. MOZ_ASSERT(from.isMemory()); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadAlignedInt32x4(toAddress(from), scratch); masm.storeAlignedInt32x4(scratch, toAddress(to)); } @@ -514,8 +514,8 @@ MoveEmitterX86::emitInt32X4Move(const MoveOperand& from, const MoveOperand& to) void MoveEmitterX86::emitFloat32X4Move(const MoveOperand& from, const MoveOperand& to) { - MOZ_ASSERT_IF(from.isFloatReg(), from.floatReg().isSimd128()); - MOZ_ASSERT_IF(to.isFloatReg(), to.floatReg().isSimd128()); + MOZ_ASSERT_IF(from.isFloatReg(), from.floatReg().isFloat32x4()); + MOZ_ASSERT_IF(to.isFloatReg(), to.floatReg().isFloat32x4()); if (from.isFloatReg()) { if (to.isFloatReg()) @@ -527,7 +527,7 @@ MoveEmitterX86::emitFloat32X4Move(const MoveOperand& from, const MoveOperand& to } else { // Memory to memory move. MOZ_ASSERT(from.isMemory()); - ScratchSimd128Scope scratch(masm); + ScratchSimdScope scratch(masm); masm.loadAlignedFloat32x4(toAddress(from), scratch); masm.storeAlignedFloat32x4(scratch, toAddress(to)); } diff --git a/js/src/jit/x86/Assembler-x86.h b/js/src/jit/x86/Assembler-x86.h index eb796c9ab1b..f8ca5d1da8b 100644 --- a/js/src/jit/x86/Assembler-x86.h +++ b/js/src/jit/x86/Assembler-x86.h @@ -46,10 +46,12 @@ static MOZ_CONSTEXPR_VAR Register FramePointer = ebp; static MOZ_CONSTEXPR_VAR Register ReturnReg = eax; static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Single); static MOZ_CONSTEXPR_VAR FloatRegister ReturnDoubleReg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Double); -static MOZ_CONSTEXPR_VAR FloatRegister ReturnSimd128Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Simd128); +static MOZ_CONSTEXPR_VAR FloatRegister ReturnInt32x4Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Int32x4); +static MOZ_CONSTEXPR_VAR FloatRegister ReturnFloat32x4Reg = FloatRegister(X86Encoding::xmm0, FloatRegisters::Float32x4); static MOZ_CONSTEXPR_VAR FloatRegister ScratchFloat32Reg = FloatRegister(X86Encoding::xmm7, FloatRegisters::Single); static MOZ_CONSTEXPR_VAR FloatRegister ScratchDoubleReg = FloatRegister(X86Encoding::xmm7, FloatRegisters::Double); -static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimd128Reg = FloatRegister(X86Encoding::xmm7, FloatRegisters::Simd128); +static MOZ_CONSTEXPR_VAR FloatRegister ScratchSimdReg = xmm7; +static MOZ_CONSTEXPR_VAR FloatRegister ScratchInt32x4Reg = FloatRegister(X86Encoding::xmm7, FloatRegisters::Int32x4); // Avoid ebp, which is the FramePointer, which is unavailable in some modes. static MOZ_CONSTEXPR_VAR Register ArgumentsRectifierReg = esi; diff --git a/js/src/jit/x86/CodeGenerator-x86.cpp b/js/src/jit/x86/CodeGenerator-x86.cpp index 7fe46b047f9..83e34b912f6 100644 --- a/js/src/jit/x86/CodeGenerator-x86.cpp +++ b/js/src/jit/x86/CodeGenerator-x86.cpp @@ -419,12 +419,12 @@ CodeGeneratorX86::emitSimdLoad(LAsmJSLoadHeap* ins) // This is still in bounds, as we've checked with a manual bounds check // or we had enough space for sure when removing the bounds check. before = after; - loadSimd(type, 1, srcAddrZ, ScratchSimd128Reg); + loadSimd(type, 1, srcAddrZ, ScratchSimdReg); after = masm.size(); masm.append(AsmJSHeapAccess(before, after)); // Move ZW atop XY - masm.vmovlhps(ScratchSimd128Reg, out, out); + masm.vmovlhps(ScratchSimdReg, out, out); } else { uint32_t before = masm.size(); loadSimd(type, numElems, srcAddr, out); @@ -593,13 +593,13 @@ CodeGeneratorX86::emitSimdStore(LAsmJSStoreHeap* ins) uint32_t after = masm.size(); masm.append(AsmJSHeapAccess(before, after, maybeCmpOffset)); - masm.vmovhlps(in, ScratchSimd128Reg, ScratchSimd128Reg); + masm.vmovhlps(in, ScratchSimdReg, ScratchSimdReg); // Store Z (W is zeroed) // This is still in bounds, as we've checked with a manual bounds check // or we had enough space for sure when removing the bounds check. before = masm.size(); - storeSimd(type, 1, ScratchSimd128Reg, dstAddrZ); + storeSimd(type, 1, ScratchSimdReg, dstAddrZ); after = masm.size(); masm.append(AsmJSHeapAccess(before, after)); } else { diff --git a/js/src/jit/x86/MacroAssembler-x86.cpp b/js/src/jit/x86/MacroAssembler-x86.cpp index 49f8ceed169..483b0ffcf8c 100644 --- a/js/src/jit/x86/MacroAssembler-x86.cpp +++ b/js/src/jit/x86/MacroAssembler-x86.cpp @@ -49,7 +49,7 @@ MacroAssemblerX86::convertUInt64ToDouble(Register64 src, Register temp, FloatReg // Following operation uses entire 128-bit of dest XMM register. // Currently higher 64-bit is free when we have access to lower 64-bit. MOZ_ASSERT(dest.size() == 8); - FloatRegister dest128 = FloatRegister(dest.encoding(), FloatRegisters::Simd128); + FloatRegister dest128 = FloatRegister(dest.encoding(), FloatRegisters::Int32x4); // Assume that src is represented as following: // src = 0x HHHHHHHH LLLLLLLL @@ -58,11 +58,11 @@ MacroAssemblerX86::convertUInt64ToDouble(Register64 src, Register temp, FloatReg // dest = 0x 00000000 00000000 00000000 LLLLLLLL // scratch = 0x 00000000 00000000 00000000 HHHHHHHH vmovd(src.low, dest128); - vmovd(src.high, ScratchSimd128Reg); + vmovd(src.high, ScratchInt32x4Reg); // Unpack and interleave dest and scratch to dest: // dest = 0x 00000000 00000000 HHHHHHHH LLLLLLLL - vpunpckldq(ScratchSimd128Reg, dest128, dest128); + vpunpckldq(ScratchInt32x4Reg, dest128, dest128); // Unpack and interleave dest and a constant C1 to dest: // C1 = 0x 00000000 00000000 45300000 43300000