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Bug 1157934 - import v8's ARM disassembler. r=jandem
This commit is contained in:
Lars T Hansen
parent
7c63227d63
commit
23cef29978
@ -3081,8 +3081,10 @@ elif test "$JS_SIMULATOR" = arm; then
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fi
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AC_DEFINE(JS_SIMULATOR)
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AC_DEFINE(JS_SIMULATOR_ARM)
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AC_DEFINE(JS_DISASM_ARM)
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AC_DEFINE(JS_CODEGEN_ARM)
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JS_SIMULATOR_ARM=1
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JS_DISASM_ARM=1
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JS_CODEGEN_ARM=1
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elif test "$JS_SIMULATOR" = arm64; then
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if test "$CPU_ARCH" != "x86_64"; then
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@ -3116,6 +3118,10 @@ elif test "$CPU_ARCH" = "x86_64"; then
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elif test "$CPU_ARCH" = "arm"; then
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AC_DEFINE(JS_CODEGEN_ARM)
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JS_CODEGEN_ARM=1
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if test -n "$MOZ_DEBUG"; then
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AC_DEFINE(JS_DISASM_ARM)
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JS_DISASM_ARM=1
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fi
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elif test "$CPU_ARCH" = "mips32"; then
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AC_DEFINE(JS_CODEGEN_MIPS32)
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JS_CODEGEN_MIPS32=1
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@ -3131,6 +3137,7 @@ AC_SUBST(JS_CODEGEN_MIPS32)
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AC_SUBST(JS_CODEGEN_X86)
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AC_SUBST(JS_CODEGEN_X64)
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AC_SUBST(JS_CODEGEN_NONE)
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AC_SUBST(JS_DISASM_ARM)
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AC_SUBST(ASMJS_MAY_USE_SIGNAL_HANDLERS_FOR_OOB)
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dnl ========================================================
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@ -600,20 +600,6 @@ ReadLine(const char* prompt)
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return result;
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}
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// Observe that llvm-mc may have a different name on your system. Make a symlink.
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static void
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DisassembleInstruction(uint32_t pc)
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{
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uint8_t* bytes = reinterpret_cast<uint8_t*>(pc);
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char hexbytes[256];
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sprintf(hexbytes, "0x%x 0x%x 0x%x 0x%x", bytes[0], bytes[1], bytes[2], bytes[3]);
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char llvmcmd[1024];
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sprintf(llvmcmd, "bash -c \"echo -n '%p'; echo '%s' | "
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"llvm-mc -disassemble -arch=arm -mcpu=cortex-a9 | "
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"grep -v pure_instructions | grep -v .text\"",
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reinterpret_cast<void*>(pc), hexbytes);
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system(llvmcmd);
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}
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void
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ArmDebugger::debug()
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@ -641,9 +627,24 @@ ArmDebugger::debug()
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// make them invisible to all commands.
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undoBreakpoints();
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#ifndef JS_DISASM_ARM
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static bool disasm_warning_printed = false;
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if (!disasm_warning_printed) {
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printf(" No ARM disassembler present. Enable JS_DISASM_ARM in configure.in.");
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disasm_warning_printed = true;
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}
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#endif
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while (!done && !sim_->has_bad_pc()) {
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if (last_pc != sim_->get_pc()) {
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DisassembleInstruction(sim_->get_pc());
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#ifdef JS_DISASM_ARM
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disasm::NameConverter converter;
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disasm::Disassembler dasm(converter);
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disasm::EmbeddedVector<char, disasm::ReasonableBufferSize> buffer;
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dasm.InstructionDecode(buffer,
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reinterpret_cast<uint8_t*>(sim_->get_pc()));
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printf(" 0x%08x %s\n", sim_->get_pc(), buffer.start());
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#endif
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last_pc = sim_->get_pc();
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}
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char* line = ReadLine("sim> ");
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@ -756,8 +757,11 @@ ArmDebugger::debug()
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cur++;
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}
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} else if (strcmp(cmd, "disasm") == 0 || strcmp(cmd, "di") == 0) {
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#ifdef JS_DISASM_ARM
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uint8_t* prev = nullptr;
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uint8_t* cur = nullptr;
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uint8_t* end = nullptr;
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if (argc == 1) {
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cur = reinterpret_cast<uint8_t*>(sim_->get_pc());
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end = cur + (10 * SimInstruction::kInstrSize);
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@ -789,9 +793,15 @@ ArmDebugger::debug()
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}
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}
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while (cur < end) {
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DisassembleInstruction(uint32_t(cur));
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cur += SimInstruction::kInstrSize;
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disasm::NameConverter converter;
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disasm::Disassembler dasm(converter);
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disasm::EmbeddedVector<char, disasm::ReasonableBufferSize> buffer;
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prev = cur;
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cur += dasm.InstructionDecode(buffer, cur);
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printf(" 0x%08x %s\n", reinterpret_cast<uint32_t>(prev), buffer.start());
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}
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#endif
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} else if (strcmp(cmd, "gdb") == 0) {
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printf("relinquishing control to gdb\n");
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asm("int $3");
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@ -34,6 +34,7 @@
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#include "jslock.h"
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#include "jit/arm/Architecture-arm.h"
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#include "jit/arm/disasm/Disasm-arm.h"
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#include "jit/IonTypes.h"
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namespace js {
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144
js/src/jit/arm/disasm/Constants-arm.cpp
Normal file
144
js/src/jit/arm/disasm/Constants-arm.cpp
Normal file
@ -0,0 +1,144 @@
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/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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* vim: set ts=8 sts=4 et sw=4 tw=99:
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*/
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// Copyright 2009 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#include "jit/arm/disasm/Constants-arm.h"
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#ifdef JS_DISASM_ARM
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namespace js {
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namespace jit {
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namespace disasm {
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double
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Instruction::DoubleImmedVmov() const
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{
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// Reconstruct a double from the immediate encoded in the vmov instruction.
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//
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// instruction: [xxxxxxxx,xxxxabcd,xxxxxxxx,xxxxefgh]
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// double: [aBbbbbbb,bbcdefgh,00000000,00000000,
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// 00000000,00000000,00000000,00000000]
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//
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// where B = ~b. Only the high 16 bits are affected.
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uint64_t high16;
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high16 = (Bits(17, 16) << 4) | Bits(3, 0); // xxxxxxxx,xxcdefgh.
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high16 |= (0xff * Bit(18)) << 6; // xxbbbbbb,bbxxxxxx.
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high16 |= (Bit(18) ^ 1) << 14; // xBxxxxxx,xxxxxxxx.
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high16 |= Bit(19) << 15; // axxxxxxx,xxxxxxxx.
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uint64_t imm = high16 << 48;
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double d;
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memcpy(&d, &imm, 8);
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return d;
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}
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// These register names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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const char* Registers::names_[kNumRegisters] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
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};
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// List of alias names which can be used when referring to ARM registers.
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const Registers::RegisterAlias Registers::aliases_[] = {
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{10, "sl"},
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{11, "r11"},
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{12, "r12"},
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{13, "r13"},
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{14, "r14"},
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{15, "r15"},
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{kNoRegister, NULL}
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};
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const char*
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Registers::Name(int reg)
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{
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const char* result;
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if ((0 <= reg) && (reg < kNumRegisters)) {
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result = names_[reg];
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} else {
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result = "noreg";
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}
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return result;
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}
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// Support for VFP registers s0 to s31 (d0 to d15) and d16-d31.
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// Note that "sN:sM" is the same as "dN/2" up to d15.
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// These register names are defined in a way to match the native disassembler
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// formatting. See for example the command "objdump -d <binary file>".
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const char* VFPRegisters::names_[kNumVFPRegisters] = {
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"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
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"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
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"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
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"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
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"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
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"d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
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"d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
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"d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
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};
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const char*
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VFPRegisters::Name(int reg, bool is_double)
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{
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MOZ_ASSERT((0 <= reg) && (reg < kNumVFPRegisters));
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return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)];
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}
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int
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VFPRegisters::Number(const char* name, bool* is_double)
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{
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for (int i = 0; i < kNumVFPRegisters; i++) {
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if (strcmp(names_[i], name) == 0) {
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if (i < kNumVFPSingleRegisters) {
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*is_double = false;
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return i;
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} else {
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*is_double = true;
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return i - kNumVFPSingleRegisters;
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}
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}
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}
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// No register with the requested name found.
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return kNoRegister;
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}
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int
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Registers::Number(const char* name)
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{
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// Look through the canonical names.
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for (int i = 0; i < kNumRegisters; i++) {
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if (strcmp(names_[i], name) == 0) {
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return i;
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}
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}
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// Look through the alias names.
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int i = 0;
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while (aliases_[i].reg != kNoRegister) {
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if (strcmp(aliases_[i].name, name) == 0) {
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return aliases_[i].reg;
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}
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i++;
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}
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// No register with the requested name found.
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return kNoRegister;
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}
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} // namespace disasm
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} // namespace jit
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} // namespace js
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#endif // JS_DISASM_ARM
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717
js/src/jit/arm/disasm/Constants-arm.h
Normal file
717
js/src/jit/arm/disasm/Constants-arm.h
Normal file
@ -0,0 +1,717 @@
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/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
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* vim: set ts=8 sts=4 et sw=4 tw=99:
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*/
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// Copyright 2011 the V8 project authors. All rights reserved.
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// Use of this source code is governed by a BSD-style license that can be
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// found in the LICENSE file.
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#ifndef jit_arm_disasm_Constants_arm_h
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#define jit_arm_disasm_Constants_arm_h
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#ifdef JS_DISASM_ARM
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namespace js {
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namespace jit {
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namespace disasm {
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// Constant pool marker.
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// Use UDF, the permanently undefined instruction.
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const int kConstantPoolMarkerMask = 0xfff000f0;
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const int kConstantPoolMarker = 0xe7f000f0;
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const int kConstantPoolLengthMaxMask = 0xffff;
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inline int
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EncodeConstantPoolLength(int length)
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{
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MOZ_ASSERT((length & kConstantPoolLengthMaxMask) == length);
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return ((length & 0xfff0) << 4) | (length & 0xf);
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}
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inline int
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DecodeConstantPoolLength(int instr)
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{
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MOZ_ASSERT((instr & kConstantPoolMarkerMask) == kConstantPoolMarker);
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return ((instr >> 4) & 0xfff0) | (instr & 0xf);
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}
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// Used in code age prologue - ldr(pc, MemOperand(pc, -4))
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const int kCodeAgeJumpInstruction = 0xe51ff004;
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// Number of registers in normal ARM mode.
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const int kNumRegisters = 16;
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// VFP support.
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const int kNumVFPSingleRegisters = 32;
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const int kNumVFPDoubleRegisters = 32;
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const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters;
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// PC is register 15.
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const int kPCRegister = 15;
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const int kNoRegister = -1;
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// -----------------------------------------------------------------------------
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// Conditions.
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// Defines constants and accessor classes to assemble, disassemble and
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// simulate ARM instructions.
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//
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// Section references in the code refer to the "ARM Architecture Reference
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// Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf)
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//
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// Constants for specific fields are defined in their respective named enums.
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// General constants are in an anonymous enum in class Instr.
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// Values for the condition field as defined in section A3.2
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enum Condition {
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kNoCondition = -1,
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eq = 0 << 28, // Z set Equal.
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ne = 1 << 28, // Z clear Not equal.
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cs = 2 << 28, // C set Unsigned higher or same.
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cc = 3 << 28, // C clear Unsigned lower.
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mi = 4 << 28, // N set Negative.
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pl = 5 << 28, // N clear Positive or zero.
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vs = 6 << 28, // V set Overflow.
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vc = 7 << 28, // V clear No overflow.
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hi = 8 << 28, // C set, Z clear Unsigned higher.
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ls = 9 << 28, // C clear or Z set Unsigned lower or same.
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ge = 10 << 28, // N == V Greater or equal.
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lt = 11 << 28, // N != V Less than.
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gt = 12 << 28, // Z clear, N == V Greater than.
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le = 13 << 28, // Z set or N != V Less then or equal
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al = 14 << 28, // Always.
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kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1).
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kNumberOfConditions = 16,
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// Aliases.
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hs = cs, // C set Unsigned higher or same.
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lo = cc // C clear Unsigned lower.
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};
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inline Condition
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NegateCondition(Condition cond)
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{
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MOZ_ASSERT(cond != al);
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return static_cast<Condition>(cond ^ ne);
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}
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// Commute a condition such that {a cond b == b cond' a}.
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inline Condition
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CommuteCondition(Condition cond)
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{
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switch (cond) {
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case lo:
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return hi;
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case hi:
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return lo;
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case hs:
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return ls;
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case ls:
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return hs;
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case lt:
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return gt;
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case gt:
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return lt;
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case ge:
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return le;
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case le:
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return ge;
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default:
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return cond;
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}
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}
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// -----------------------------------------------------------------------------
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// Instructions encoding.
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// Instr is merely used by the Assembler to distinguish 32bit integers
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// representing instructions from usual 32 bit values.
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// Instruction objects are pointers to 32bit values, and provide methods to
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// access the various ISA fields.
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typedef int32_t Instr;
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// Opcodes for Data-processing instructions (instructions with a type 0 and 1)
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// as defined in section A3.4
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enum Opcode {
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AND = 0 << 21, // Logical AND.
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EOR = 1 << 21, // Logical Exclusive OR.
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SUB = 2 << 21, // Subtract.
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RSB = 3 << 21, // Reverse Subtract.
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ADD = 4 << 21, // Add.
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ADC = 5 << 21, // Add with Carry.
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SBC = 6 << 21, // Subtract with Carry.
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RSC = 7 << 21, // Reverse Subtract with Carry.
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TST = 8 << 21, // Test.
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TEQ = 9 << 21, // Test Equivalence.
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CMP = 10 << 21, // Compare.
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CMN = 11 << 21, // Compare Negated.
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ORR = 12 << 21, // Logical (inclusive) OR.
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MOV = 13 << 21, // Move.
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BIC = 14 << 21, // Bit Clear.
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MVN = 15 << 21 // Move Not.
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};
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// The bits for bit 7-4 for some type 0 miscellaneous instructions.
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enum MiscInstructionsBits74 {
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// With bits 22-21 01.
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BX = 1 << 4,
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BXJ = 2 << 4,
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BLX = 3 << 4,
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BKPT = 7 << 4,
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// With bits 22-21 11.
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CLZ = 1 << 4
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};
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// Instruction encoding bits and masks.
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enum {
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H = 1 << 5, // Halfword (or byte).
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S6 = 1 << 6, // Signed (or unsigned).
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L = 1 << 20, // Load (or store).
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S = 1 << 20, // Set condition code (or leave unchanged).
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W = 1 << 21, // Writeback base register (or leave unchanged).
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A = 1 << 21, // Accumulate in multiply instruction (or not).
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B = 1 << 22, // Unsigned byte (or word).
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N = 1 << 22, // Long (or short).
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U = 1 << 23, // Positive (or negative) offset/index.
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P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing).
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I = 1 << 25, // Immediate shifter operand (or not).
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B0 = 1 << 0,
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B4 = 1 << 4,
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B5 = 1 << 5,
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B6 = 1 << 6,
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B7 = 1 << 7,
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B8 = 1 << 8,
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B9 = 1 << 9,
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B12 = 1 << 12,
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B16 = 1 << 16,
|
||||
B17 = 1 << 17,
|
||||
B18 = 1 << 18,
|
||||
B19 = 1 << 19,
|
||||
B20 = 1 << 20,
|
||||
B21 = 1 << 21,
|
||||
B22 = 1 << 22,
|
||||
B23 = 1 << 23,
|
||||
B24 = 1 << 24,
|
||||
B25 = 1 << 25,
|
||||
B26 = 1 << 26,
|
||||
B27 = 1 << 27,
|
||||
B28 = 1 << 28,
|
||||
|
||||
// Instruction bit masks.
|
||||
kCondMask = 15 << 28,
|
||||
kALUMask = 0x6f << 21,
|
||||
kRdMask = 15 << 12, // In str instruction.
|
||||
kCoprocessorMask = 15 << 8,
|
||||
kOpCodeMask = 15 << 21, // In data-processing instructions.
|
||||
kImm24Mask = (1 << 24) - 1,
|
||||
kImm16Mask = (1 << 16) - 1,
|
||||
kImm8Mask = (1 << 8) - 1,
|
||||
kOff12Mask = (1 << 12) - 1,
|
||||
kOff8Mask = (1 << 8) - 1
|
||||
};
|
||||
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// Addressing modes and instruction variants.
|
||||
|
||||
// Condition code updating mode.
|
||||
enum SBit {
|
||||
SetCC = 1 << 20, // Set condition code.
|
||||
LeaveCC = 0 << 20 // Leave condition code unchanged.
|
||||
};
|
||||
|
||||
|
||||
// Status register selection.
|
||||
enum SRegister {
|
||||
CPSR = 0 << 22,
|
||||
SPSR = 1 << 22
|
||||
};
|
||||
|
||||
|
||||
// Shifter types for Data-processing operands as defined in section A5.1.2.
|
||||
enum ShiftOp {
|
||||
LSL = 0 << 5, // Logical shift left.
|
||||
LSR = 1 << 5, // Logical shift right.
|
||||
ASR = 2 << 5, // Arithmetic shift right.
|
||||
ROR = 3 << 5, // Rotate right.
|
||||
|
||||
// RRX is encoded as ROR with shift_imm == 0.
|
||||
// Use a special code to make the distinction. The RRX ShiftOp is only used
|
||||
// as an argument, and will never actually be encoded. The Assembler will
|
||||
// detect it and emit the correct ROR shift operand with shift_imm == 0.
|
||||
RRX = -1,
|
||||
kNumberOfShifts = 4
|
||||
};
|
||||
|
||||
|
||||
// Status register fields.
|
||||
enum SRegisterField {
|
||||
CPSR_c = CPSR | 1 << 16,
|
||||
CPSR_x = CPSR | 1 << 17,
|
||||
CPSR_s = CPSR | 1 << 18,
|
||||
CPSR_f = CPSR | 1 << 19,
|
||||
SPSR_c = SPSR | 1 << 16,
|
||||
SPSR_x = SPSR | 1 << 17,
|
||||
SPSR_s = SPSR | 1 << 18,
|
||||
SPSR_f = SPSR | 1 << 19
|
||||
};
|
||||
|
||||
// Status register field mask (or'ed SRegisterField enum values).
|
||||
typedef uint32_t SRegisterFieldMask;
|
||||
|
||||
|
||||
// Memory operand addressing mode.
|
||||
enum AddrMode {
|
||||
// Bit encoding P U W.
|
||||
Offset = (8|4|0) << 21, // Offset (without writeback to base).
|
||||
PreIndex = (8|4|1) << 21, // Pre-indexed addressing with writeback.
|
||||
PostIndex = (0|4|0) << 21, // Post-indexed addressing with writeback.
|
||||
NegOffset = (8|0|0) << 21, // Negative offset (without writeback to base).
|
||||
NegPreIndex = (8|0|1) << 21, // Negative pre-indexed with writeback.
|
||||
NegPostIndex = (0|0|0) << 21 // Negative post-indexed with writeback.
|
||||
};
|
||||
|
||||
|
||||
// Load/store multiple addressing mode.
|
||||
enum BlockAddrMode {
|
||||
// Bit encoding P U W .
|
||||
da = (0|0|0) << 21, // Decrement after.
|
||||
ia = (0|4|0) << 21, // Increment after.
|
||||
db = (8|0|0) << 21, // Decrement before.
|
||||
ib = (8|4|0) << 21, // Increment before.
|
||||
da_w = (0|0|1) << 21, // Decrement after with writeback to base.
|
||||
ia_w = (0|4|1) << 21, // Increment after with writeback to base.
|
||||
db_w = (8|0|1) << 21, // Decrement before with writeback to base.
|
||||
ib_w = (8|4|1) << 21, // Increment before with writeback to base.
|
||||
|
||||
// Alias modes for comparison when writeback does not matter.
|
||||
da_x = (0|0|0) << 21, // Decrement after.
|
||||
ia_x = (0|4|0) << 21, // Increment after.
|
||||
db_x = (8|0|0) << 21, // Decrement before.
|
||||
ib_x = (8|4|0) << 21, // Increment before.
|
||||
|
||||
kBlockAddrModeMask = (8|4|1) << 21
|
||||
};
|
||||
|
||||
|
||||
// Coprocessor load/store operand size.
|
||||
enum LFlag {
|
||||
Long = 1 << 22, // Long load/store coprocessor.
|
||||
Short = 0 << 22 // Short load/store coprocessor.
|
||||
};
|
||||
|
||||
|
||||
// NEON data type
|
||||
enum NeonDataType {
|
||||
NeonS8 = 0x1, // U = 0, imm3 = 0b001
|
||||
NeonS16 = 0x2, // U = 0, imm3 = 0b010
|
||||
NeonS32 = 0x4, // U = 0, imm3 = 0b100
|
||||
NeonU8 = 1 << 24 | 0x1, // U = 1, imm3 = 0b001
|
||||
NeonU16 = 1 << 24 | 0x2, // U = 1, imm3 = 0b010
|
||||
NeonU32 = 1 << 24 | 0x4, // U = 1, imm3 = 0b100
|
||||
NeonDataTypeSizeMask = 0x7,
|
||||
NeonDataTypeUMask = 1 << 24
|
||||
};
|
||||
|
||||
enum NeonListType {
|
||||
nlt_1 = 0x7,
|
||||
nlt_2 = 0xA,
|
||||
nlt_3 = 0x6,
|
||||
nlt_4 = 0x2
|
||||
};
|
||||
|
||||
enum NeonSize {
|
||||
Neon8 = 0x0,
|
||||
Neon16 = 0x1,
|
||||
Neon32 = 0x2,
|
||||
Neon64 = 0x3
|
||||
};
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// Supervisor Call (svc) specific support.
|
||||
|
||||
// Special Software Interrupt codes when used in the presence of the ARM
|
||||
// simulator.
|
||||
// svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for
|
||||
// standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
|
||||
enum SoftwareInterruptCodes {
|
||||
// transition to C code
|
||||
kCallRtRedirected = 0x10,
|
||||
// break point
|
||||
kBreakpoint = 0x20,
|
||||
// stop
|
||||
kStopCode = 1 << 23
|
||||
};
|
||||
const uint32_t kStopCodeMask = kStopCode - 1;
|
||||
const uint32_t kMaxStopCode = kStopCode - 1;
|
||||
const int32_t kDefaultStopCode = -1;
|
||||
|
||||
|
||||
// Type of VFP register. Determines register encoding.
|
||||
enum VFPRegPrecision {
|
||||
kSinglePrecision = 0,
|
||||
kDoublePrecision = 1
|
||||
};
|
||||
|
||||
|
||||
// VFP FPSCR constants.
|
||||
enum VFPConversionMode {
|
||||
kFPSCRRounding = 0,
|
||||
kDefaultRoundToZero = 1
|
||||
};
|
||||
|
||||
// This mask does not include the "inexact" or "input denormal" cumulative
|
||||
// exceptions flags, because we usually don't want to check for it.
|
||||
const uint32_t kVFPExceptionMask = 0xf;
|
||||
const uint32_t kVFPInvalidOpExceptionBit = 1 << 0;
|
||||
const uint32_t kVFPOverflowExceptionBit = 1 << 2;
|
||||
const uint32_t kVFPUnderflowExceptionBit = 1 << 3;
|
||||
const uint32_t kVFPInexactExceptionBit = 1 << 4;
|
||||
const uint32_t kVFPFlushToZeroMask = 1 << 24;
|
||||
const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25;
|
||||
|
||||
const uint32_t kVFPNConditionFlagBit = 1 << 31;
|
||||
const uint32_t kVFPZConditionFlagBit = 1 << 30;
|
||||
const uint32_t kVFPCConditionFlagBit = 1 << 29;
|
||||
const uint32_t kVFPVConditionFlagBit = 1 << 28;
|
||||
|
||||
|
||||
// VFP rounding modes. See ARM DDI 0406B Page A2-29.
|
||||
enum VFPRoundingMode {
|
||||
RN = 0 << 22, // Round to Nearest.
|
||||
RP = 1 << 22, // Round towards Plus Infinity.
|
||||
RM = 2 << 22, // Round towards Minus Infinity.
|
||||
RZ = 3 << 22, // Round towards zero.
|
||||
|
||||
// Aliases.
|
||||
kRoundToNearest = RN,
|
||||
kRoundToPlusInf = RP,
|
||||
kRoundToMinusInf = RM,
|
||||
kRoundToZero = RZ
|
||||
};
|
||||
|
||||
const uint32_t kVFPRoundingModeMask = 3 << 22;
|
||||
|
||||
enum CheckForInexactConversion {
|
||||
kCheckForInexactConversion,
|
||||
kDontCheckForInexactConversion
|
||||
};
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// Hints.
|
||||
|
||||
// Branch hints are not used on the ARM. They are defined so that they can
|
||||
// appear in shared function signatures, but will be ignored in ARM
|
||||
// implementations.
|
||||
enum Hint { no_hint };
|
||||
|
||||
// Hints are not used on the arm. Negating is trivial.
|
||||
inline Hint
|
||||
NegateHint(Hint ignored)
|
||||
{
|
||||
return no_hint;
|
||||
}
|
||||
|
||||
|
||||
// -----------------------------------------------------------------------------
|
||||
// Instruction abstraction.
|
||||
|
||||
// The class Instruction enables access to individual fields defined in the ARM
|
||||
// architecture instruction set encoding as described in figure A3-1.
|
||||
// Note that the Assembler uses typedef int32_t Instr.
|
||||
//
|
||||
// Example: Test whether the instruction at ptr does set the condition code
|
||||
// bits.
|
||||
//
|
||||
// bool InstructionSetsConditionCodes(byte* ptr) {
|
||||
// Instruction* instr = Instruction::At(ptr);
|
||||
// int type = instr->TypeValue();
|
||||
// return ((type == 0) || (type == 1)) && instr->HasS();
|
||||
// }
|
||||
//
|
||||
class Instruction {
|
||||
public:
|
||||
enum {
|
||||
kInstrSize = 4,
|
||||
kInstrSizeLog2 = 2,
|
||||
kPCReadOffset = 8
|
||||
};
|
||||
|
||||
// Helper macro to define static accessors.
|
||||
// We use the cast to char* trick to bypass the strict anti-aliasing rules.
|
||||
#define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \
|
||||
static inline return_type Name(Instr instr) { \
|
||||
char* temp = reinterpret_cast<char*>(&instr); \
|
||||
return reinterpret_cast<Instruction*>(temp)->Name(); \
|
||||
}
|
||||
|
||||
#define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name)
|
||||
|
||||
// Get the raw instruction bits.
|
||||
inline Instr InstructionBits() const {
|
||||
return *reinterpret_cast<const Instr*>(this);
|
||||
}
|
||||
|
||||
// Set the raw instruction bits to value.
|
||||
inline void SetInstructionBits(Instr value) {
|
||||
*reinterpret_cast<Instr*>(this) = value;
|
||||
}
|
||||
|
||||
// Read one particular bit out of the instruction bits.
|
||||
inline int Bit(int nr) const {
|
||||
return (InstructionBits() >> nr) & 1;
|
||||
}
|
||||
|
||||
// Read a bit field's value out of the instruction bits.
|
||||
inline int Bits(int hi, int lo) const {
|
||||
return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1);
|
||||
}
|
||||
|
||||
// Read a bit field out of the instruction bits.
|
||||
inline int BitField(int hi, int lo) const {
|
||||
return InstructionBits() & (((2 << (hi - lo)) - 1) << lo);
|
||||
}
|
||||
|
||||
// Static support.
|
||||
|
||||
// Read one particular bit out of the instruction bits.
|
||||
static inline int Bit(Instr instr, int nr) {
|
||||
return (instr >> nr) & 1;
|
||||
}
|
||||
|
||||
// Read the value of a bit field out of the instruction bits.
|
||||
static inline int Bits(Instr instr, int hi, int lo) {
|
||||
return (instr >> lo) & ((2 << (hi - lo)) - 1);
|
||||
}
|
||||
|
||||
|
||||
// Read a bit field out of the instruction bits.
|
||||
static inline int BitField(Instr instr, int hi, int lo) {
|
||||
return instr & (((2 << (hi - lo)) - 1) << lo);
|
||||
}
|
||||
|
||||
|
||||
// Accessors for the different named fields used in the ARM encoding.
|
||||
// The naming of these accessor corresponds to figure A3-1.
|
||||
//
|
||||
// Two kind of accessors are declared:
|
||||
// - <Name>Field() will return the raw field, i.e. the field's bits at their
|
||||
// original place in the instruction encoding.
|
||||
// e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
|
||||
// 0xC0810002 ConditionField(instr) will return 0xC0000000.
|
||||
// - <Name>Value() will return the field value, shifted back to bit 0.
|
||||
// e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
|
||||
// 0xC0810002 ConditionField(instr) will return 0xC.
|
||||
|
||||
|
||||
// Generally applicable fields
|
||||
inline Condition ConditionValue() const {
|
||||
return static_cast<Condition>(Bits(31, 28));
|
||||
}
|
||||
inline Condition ConditionField() const {
|
||||
return static_cast<Condition>(BitField(31, 28));
|
||||
}
|
||||
DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue);
|
||||
DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField);
|
||||
|
||||
inline int TypeValue() const { return Bits(27, 25); }
|
||||
inline int SpecialValue() const { return Bits(27, 23); }
|
||||
|
||||
inline int RnValue() const { return Bits(19, 16); }
|
||||
DECLARE_STATIC_ACCESSOR(RnValue);
|
||||
inline int RdValue() const { return Bits(15, 12); }
|
||||
DECLARE_STATIC_ACCESSOR(RdValue);
|
||||
|
||||
inline int CoprocessorValue() const { return Bits(11, 8); }
|
||||
// Support for VFP.
|
||||
// Vn(19-16) | Vd(15-12) | Vm(3-0)
|
||||
inline int VnValue() const { return Bits(19, 16); }
|
||||
inline int VmValue() const { return Bits(3, 0); }
|
||||
inline int VdValue() const { return Bits(15, 12); }
|
||||
inline int NValue() const { return Bit(7); }
|
||||
inline int MValue() const { return Bit(5); }
|
||||
inline int DValue() const { return Bit(22); }
|
||||
inline int RtValue() const { return Bits(15, 12); }
|
||||
inline int PValue() const { return Bit(24); }
|
||||
inline int UValue() const { return Bit(23); }
|
||||
inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); }
|
||||
inline int Opc2Value() const { return Bits(19, 16); }
|
||||
inline int Opc3Value() const { return Bits(7, 6); }
|
||||
inline int SzValue() const { return Bit(8); }
|
||||
inline int VLValue() const { return Bit(20); }
|
||||
inline int VCValue() const { return Bit(8); }
|
||||
inline int VAValue() const { return Bits(23, 21); }
|
||||
inline int VBValue() const { return Bits(6, 5); }
|
||||
inline int VFPNRegValue(VFPRegPrecision pre) {
|
||||
return VFPGlueRegValue(pre, 16, 7);
|
||||
}
|
||||
inline int VFPMRegValue(VFPRegPrecision pre) {
|
||||
return VFPGlueRegValue(pre, 0, 5);
|
||||
}
|
||||
inline int VFPDRegValue(VFPRegPrecision pre) {
|
||||
return VFPGlueRegValue(pre, 12, 22);
|
||||
}
|
||||
|
||||
// Fields used in Data processing instructions
|
||||
inline int OpcodeValue() const {
|
||||
return static_cast<Opcode>(Bits(24, 21));
|
||||
}
|
||||
inline Opcode OpcodeField() const {
|
||||
return static_cast<Opcode>(BitField(24, 21));
|
||||
}
|
||||
inline int SValue() const { return Bit(20); }
|
||||
// with register
|
||||
inline int RmValue() const { return Bits(3, 0); }
|
||||
DECLARE_STATIC_ACCESSOR(RmValue);
|
||||
inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
|
||||
inline ShiftOp ShiftField() const {
|
||||
return static_cast<ShiftOp>(BitField(6, 5));
|
||||
}
|
||||
inline int RegShiftValue() const { return Bit(4); }
|
||||
inline int RsValue() const { return Bits(11, 8); }
|
||||
inline int ShiftAmountValue() const { return Bits(11, 7); }
|
||||
// with immediate
|
||||
inline int RotateValue() const { return Bits(11, 8); }
|
||||
DECLARE_STATIC_ACCESSOR(RotateValue);
|
||||
inline int Immed8Value() const { return Bits(7, 0); }
|
||||
DECLARE_STATIC_ACCESSOR(Immed8Value);
|
||||
inline int Immed4Value() const { return Bits(19, 16); }
|
||||
inline int ImmedMovwMovtValue() const {
|
||||
return Immed4Value() << 12 | Offset12Value(); }
|
||||
DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue);
|
||||
|
||||
// Fields used in Load/Store instructions
|
||||
inline int PUValue() const { return Bits(24, 23); }
|
||||
inline int PUField() const { return BitField(24, 23); }
|
||||
inline int BValue() const { return Bit(22); }
|
||||
inline int WValue() const { return Bit(21); }
|
||||
inline int LValue() const { return Bit(20); }
|
||||
// with register uses same fields as Data processing instructions above
|
||||
// with immediate
|
||||
inline int Offset12Value() const { return Bits(11, 0); }
|
||||
// multiple
|
||||
inline int RlistValue() const { return Bits(15, 0); }
|
||||
// extra loads and stores
|
||||
inline int SignValue() const { return Bit(6); }
|
||||
inline int HValue() const { return Bit(5); }
|
||||
inline int ImmedHValue() const { return Bits(11, 8); }
|
||||
inline int ImmedLValue() const { return Bits(3, 0); }
|
||||
|
||||
// Fields used in Branch instructions
|
||||
inline int LinkValue() const { return Bit(24); }
|
||||
inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); }
|
||||
|
||||
// Fields used in Software interrupt instructions
|
||||
inline SoftwareInterruptCodes SvcValue() const {
|
||||
return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
|
||||
}
|
||||
|
||||
// Test for special encodings of type 0 instructions (extra loads and stores,
|
||||
// as well as multiplications).
|
||||
inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
|
||||
|
||||
// Test for miscellaneous instructions encodings of type 0 instructions.
|
||||
inline bool IsMiscType0() const { return (Bit(24) == 1)
|
||||
&& (Bit(23) == 0)
|
||||
&& (Bit(20) == 0)
|
||||
&& ((Bit(7) == 0)); }
|
||||
|
||||
// Test for a nop instruction, which falls under type 1.
|
||||
inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; }
|
||||
|
||||
// Test for a stop instruction.
|
||||
inline bool IsStop() const {
|
||||
return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode);
|
||||
}
|
||||
|
||||
// Special accessors that test for existence of a value.
|
||||
inline bool HasS() const { return SValue() == 1; }
|
||||
inline bool HasB() const { return BValue() == 1; }
|
||||
inline bool HasW() const { return WValue() == 1; }
|
||||
inline bool HasL() const { return LValue() == 1; }
|
||||
inline bool HasU() const { return UValue() == 1; }
|
||||
inline bool HasSign() const { return SignValue() == 1; }
|
||||
inline bool HasH() const { return HValue() == 1; }
|
||||
inline bool HasLink() const { return LinkValue() == 1; }
|
||||
|
||||
// Decoding the double immediate in the vmov instruction.
|
||||
double DoubleImmedVmov() const;
|
||||
|
||||
// Instructions are read of out a code stream. The only way to get a
|
||||
// reference to an instruction is to convert a pointer. There is no way
|
||||
// to allocate or create instances of class Instruction.
|
||||
// Use the At(pc) function to create references to Instruction.
|
||||
static Instruction* At(uint8_t* pc) {
|
||||
return reinterpret_cast<Instruction*>(pc);
|
||||
}
|
||||
|
||||
|
||||
private:
|
||||
// Join split register codes, depending on single or double precision.
|
||||
// four_bit is the position of the least-significant bit of the four
|
||||
// bit specifier. one_bit is the position of the additional single bit
|
||||
// specifier.
|
||||
inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) {
|
||||
if (pre == kSinglePrecision) {
|
||||
return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit);
|
||||
}
|
||||
return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit);
|
||||
}
|
||||
|
||||
// We need to prevent the creation of instances of class Instruction.
|
||||
Instruction() = delete;
|
||||
Instruction(const Instruction&) = delete;
|
||||
void operator=(const Instruction&) = delete;
|
||||
};
|
||||
|
||||
|
||||
// Helper functions for converting between register numbers and names.
|
||||
class Registers {
|
||||
public:
|
||||
// Return the name of the register.
|
||||
static const char* Name(int reg);
|
||||
|
||||
// Lookup the register number for the name provided.
|
||||
static int Number(const char* name);
|
||||
|
||||
struct RegisterAlias {
|
||||
int reg;
|
||||
const char* name;
|
||||
};
|
||||
|
||||
private:
|
||||
static const char* names_[kNumRegisters];
|
||||
static const RegisterAlias aliases_[];
|
||||
};
|
||||
|
||||
// Helper functions for converting between VFP register numbers and names.
|
||||
class VFPRegisters {
|
||||
public:
|
||||
// Return the name of the register.
|
||||
static const char* Name(int reg, bool is_double);
|
||||
|
||||
// Lookup the register number for the name provided.
|
||||
// Set flag pointed by is_double to true if register
|
||||
// is double-precision.
|
||||
static int Number(const char* name, bool* is_double);
|
||||
|
||||
private:
|
||||
static const char* names_[kNumVFPRegisters];
|
||||
};
|
||||
|
||||
|
||||
} // namespace disasm
|
||||
} // namespace jit
|
||||
} // namespace js
|
||||
|
||||
#endif // JS_DISASM_ARM
|
||||
|
||||
#endif // jit_arm_disasm_Constants_arm_h
|
||||
2108
js/src/jit/arm/disasm/Disasm-arm.cpp
Normal file
2108
js/src/jit/arm/disasm/Disasm-arm.cpp
Normal file
File diff suppressed because it is too large
Load Diff
138
js/src/jit/arm/disasm/Disasm-arm.h
Normal file
138
js/src/jit/arm/disasm/Disasm-arm.h
Normal file
@ -0,0 +1,138 @@
|
||||
/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 4 -*-
|
||||
* vim: set ts=8 sts=4 et sw=4 tw=99:
|
||||
*/
|
||||
// Copyright 2007-2008 the V8 project authors. All rights reserved.
|
||||
// Use of this source code is governed by a BSD-style license that can be
|
||||
// found in the LICENSE file.
|
||||
|
||||
#ifndef jit_arm_disasm_Disasm_arm_h
|
||||
#define jit_arm_disasm_Disasm_arm_h
|
||||
|
||||
#ifdef JS_DISASM_ARM
|
||||
|
||||
namespace js {
|
||||
namespace jit {
|
||||
namespace disasm {
|
||||
|
||||
typedef unsigned char byte;
|
||||
|
||||
// A reasonable (ie, safe) buffer size for the disassembly of a single instruction.
|
||||
const int ReasonableBufferSize = 256;
|
||||
|
||||
// Vector as used by the original code to allow for minimal modification.
|
||||
// Functions exactly like a character array with helper methods.
|
||||
template <typename T>
|
||||
class V8Vector {
|
||||
public:
|
||||
V8Vector() : start_(nullptr), length_(0) {}
|
||||
V8Vector(T* data, int length) : start_(data), length_(length) {
|
||||
MOZ_ASSERT(length == 0 || (length > 0 && data != nullptr));
|
||||
}
|
||||
|
||||
// Returns the length of the vector.
|
||||
int length() const { return length_; }
|
||||
|
||||
// Returns the pointer to the start of the data in the vector.
|
||||
T* start() const { return start_; }
|
||||
|
||||
// Access individual vector elements - checks bounds in debug mode.
|
||||
T& operator[](int index) const {
|
||||
MOZ_ASSERT(0 <= index && index < length_);
|
||||
return start_[index];
|
||||
}
|
||||
|
||||
inline V8Vector<T> operator+(int offset) {
|
||||
MOZ_ASSERT(offset < length_);
|
||||
return V8Vector<T>(start_ + offset, length_ - offset);
|
||||
}
|
||||
|
||||
private:
|
||||
T* start_;
|
||||
int length_;
|
||||
};
|
||||
|
||||
|
||||
template <typename T, int kSize>
|
||||
class EmbeddedVector : public V8Vector<T> {
|
||||
public:
|
||||
EmbeddedVector() : V8Vector<T>(buffer_, kSize) { }
|
||||
|
||||
explicit EmbeddedVector(T initial_value) : V8Vector<T>(buffer_, kSize) {
|
||||
for (int i = 0; i < kSize; ++i) {
|
||||
buffer_[i] = initial_value;
|
||||
}
|
||||
}
|
||||
|
||||
// When copying, make underlying Vector to reference our buffer.
|
||||
EmbeddedVector(const EmbeddedVector& rhs)
|
||||
: V8Vector<T>(rhs) {
|
||||
MemCopy(buffer_, rhs.buffer_, sizeof(T) * kSize);
|
||||
this->set_start(buffer_);
|
||||
}
|
||||
|
||||
EmbeddedVector& operator=(const EmbeddedVector& rhs) {
|
||||
if (this == &rhs) return *this;
|
||||
V8Vector<T>::operator=(rhs);
|
||||
MemCopy(buffer_, rhs.buffer_, sizeof(T) * kSize);
|
||||
this->set_start(buffer_);
|
||||
return *this;
|
||||
}
|
||||
|
||||
private:
|
||||
T buffer_[kSize];
|
||||
};
|
||||
|
||||
|
||||
// Interface and default implementation for converting addresses and
|
||||
// register-numbers to text. The default implementation is machine
|
||||
// specific.
|
||||
class NameConverter {
|
||||
public:
|
||||
virtual ~NameConverter() {}
|
||||
virtual const char* NameOfCPURegister(int reg) const;
|
||||
virtual const char* NameOfByteCPURegister(int reg) const;
|
||||
virtual const char* NameOfXMMRegister(int reg) const;
|
||||
virtual const char* NameOfAddress(byte* addr) const;
|
||||
virtual const char* NameOfConstant(byte* addr) const;
|
||||
virtual const char* NameInCode(byte* addr) const;
|
||||
|
||||
protected:
|
||||
EmbeddedVector<char, 128> tmp_buffer_;
|
||||
};
|
||||
|
||||
|
||||
// A generic Disassembler interface
|
||||
class Disassembler {
|
||||
public:
|
||||
// Caller deallocates converter.
|
||||
explicit Disassembler(const NameConverter& converter);
|
||||
|
||||
virtual ~Disassembler();
|
||||
|
||||
// Writes one disassembled instruction into 'buffer' (0-terminated).
|
||||
// Returns the length of the disassembled machine instruction in bytes.
|
||||
int InstructionDecode(V8Vector<char> buffer, uint8_t* instruction);
|
||||
|
||||
// Returns -1 if instruction does not mark the beginning of a constant pool,
|
||||
// or the number of entries in the constant pool beginning here.
|
||||
int ConstantPoolSizeAt(byte* instruction);
|
||||
|
||||
// Write disassembly into specified file 'f' using specified NameConverter
|
||||
// (see constructor).
|
||||
static void Disassemble(FILE* f, uint8_t* begin, uint8_t* end);
|
||||
private:
|
||||
const NameConverter& converter_;
|
||||
|
||||
// Disallow implicit constructors.
|
||||
Disassembler() = delete;
|
||||
Disassembler(const Disassembler&) = delete;
|
||||
void operator=(const Disassembler&) = delete;
|
||||
};
|
||||
|
||||
} // namespace disasm
|
||||
} // namespace jit
|
||||
} // namespace js
|
||||
|
||||
#endif // JS_DISASM_ARM
|
||||
|
||||
#endif // jit_arm_disasm_Disasm_arm_h
|
||||
@ -417,6 +417,8 @@ elif CONFIG['JS_CODEGEN_ARM']:
|
||||
'jit/arm/BaselineCompiler-arm.cpp',
|
||||
'jit/arm/BaselineIC-arm.cpp',
|
||||
'jit/arm/CodeGenerator-arm.cpp',
|
||||
'jit/arm/disasm/Constants-arm.cpp',
|
||||
'jit/arm/disasm/Disasm-arm.cpp',
|
||||
'jit/arm/Lowering-arm.cpp',
|
||||
'jit/arm/MacroAssembler-arm.cpp',
|
||||
'jit/arm/MoveEmitter-arm.cpp',
|
||||
|
||||
Loading…
Reference in New Issue
Block a user