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Implement LIR_stb on PPC32/64 (bug 558597 r=rreitmai+)

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Patch also fixes an invalid assert that required load/store
displacements to be multiples of 4 on PPC.

--HG--
extra : convert_revision : e2a7f626b35179db953469ea94cdb39d16b10f7c
This commit is contained in:
Edwin Smith 2010-04-12 21:27:19 -04:00
parent 4634603bd4
commit 176d926d8c
2 changed files with 26 additions and 4 deletions
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20
js/src/nanojit/NativePPC.cpp
View File

@ -178,9 +178,9 @@ namespace nanojit
switch (op) {
case LIR_sti:
case LIR_stb:
// handled by mainline code below for now
break;
case LIR_stb:
case LIR_sts:
NanoAssertMsg(0, "NJ_EXPANDED_LOADSTORE_SUPPORTED not yet supported for this architecture");
return;
@ -194,13 +194,27 @@ namespace nanojit
#if !PEDANTIC
if (isS16(dr)) {
STW(rs, dr, ra);
switch (op) {
case LIR_sti:
STW(rs, dr, ra);
break;
case LIR_stb:
STB(rs, dr, ra);
break;
}
return;
}
#endif
// general case store, any offset size
STWX(rs, ra, R0);
switch (op) {
case LIR_sti:
STWX(rs, ra, R0);
break;
case LIR_stb:
STBX(rs, ra, R0);
break;
}
asm_li(R0, dr);
}

10
js/src/nanojit/NativePPC.h
View File

@ -226,6 +226,8 @@ namespace nanojit
PPC_srawi = 0x7C000670, // shift right algebraic word immediate
PPC_srd = 0x7C000436, // shift right doubleword (zero ext)
PPC_srw = 0x7C000430, // shift right word (zero ext)
PPC_stb = 0x98000000, // store byte
PPC_stbx = 0x7C0001AE, // store byte indexed
PPC_std = 0xF8000000, // store doubleword
PPC_stdu = 0xF8000001, // store doubleword with update
PPC_stdux = 0x7C00016A, // store doubleword with update indexed
@ -437,7 +439,7 @@ namespace nanojit
#define MFCTR(r) MFSPR(r, ctr)
#define MEMd(op, r, d, a) do {\
NanoAssert(isS16(d) && (d&3)==0);\
NanoAssert(isS16(d));\
EMIT1(PPC_##op | GPR(r)<<21 | GPR(a)<<16 | uint16_t(d), "%s %s,%d(%s)", #op, gpn(r), int16_t(d), gpn(a));\
} while(0) /* no addr */
@ -463,11 +465,17 @@ namespace nanojit
#define LWZX(r, a, b) MEMx(lwzx, r, a, b)
#define LDX(r, a, b) MEMx(ldx, r, a, b)
// store word (32-bit integer)
#define STW(r, d, b) MEMd(stw, r, d, b)
#define STWU(r, d, b) MEMd(stwu, r, d, b)
#define STWX(s, a, b) MEMx(stwx, s, a, b)
#define STWUX(s, a, b) MEMux(stwux, s, a, b)
// store byte
#define STB(r, d, b) MEMd(stb, r, d, b)
#define STBX(s, a, b) MEMx(stbx, s, a, b)
// store double (64-bit float)
#define STD(r, d, b) MEMd(std, r, d, b)
#define STDU(r, d, b) MEMd(stdu, r, d, b)
#define STDX(s, a, b) MEMx(stdx, s, a, b)