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Bug 829352 - Add IonMacroAssembler methods for generating addPtr, subPtr, xorPtr, and addPtr variants. r=nbp

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This commit is contained in:
Kannan Vijayan 2013-01-11 12:53:58 -05:00
parent 54f28b4875
commit 138b770127
6 changed files with 102 additions and 2 deletions
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20
js/src/assembler/assembler/X86Assembler.h
View File

@ -502,10 +502,18 @@ public:
#if WTF_CPU_X86_64
void addq_rr(RegisterID src, RegisterID dst)
{
FIXME_INSN_PRINTING;
spew("addq %s, %s",
nameIReg(8,src), nameIReg(8,dst));
m_formatter.oneByteOp64(OP_ADD_EvGv, src, dst);
}
void addq_mr(int offset, RegisterID base, RegisterID dst)
{
spew("addq %s0x%x(%s), %s",
PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst));
m_formatter.oneByteOp64(OP_ADD_GvEv, dst, base, offset);
}
void addq_ir(int imm, RegisterID dst)
{
spew("addq $0x%x, %s", imm, nameIReg(8,dst));
@ -800,10 +808,18 @@ public:
#if WTF_CPU_X86_64
void subq_rr(RegisterID src, RegisterID dst)
{
FIXME_INSN_PRINTING;
spew("subq %s, %s",
nameIReg(8,src), nameIReg(8,dst));
m_formatter.oneByteOp64(OP_SUB_EvGv, src, dst);
}
void subq_mr(int offset, RegisterID base, RegisterID dst)
{
spew("subq %s0x%x(%s), %s",
PRETTY_PRINT_OFFSET(offset), nameIReg(8,base), nameIReg(8,dst));
m_formatter.oneByteOp64(OP_SUB_GvEv, dst, base, offset);
}
void subq_ir(int imm, RegisterID dst)
{
spew("subq $0x%x, %s", imm, nameIReg(8,dst));

26
js/src/ion/arm/MacroAssembler-arm.cpp
View File

@ -1482,6 +1482,13 @@ MacroAssemblerARMCompat::addPtr(Register src, Register dest)
ma_add(src, dest);
}
void
MacroAssemblerARMCompat::addPtr(const Address &src, Register dest)
{
load32(src, ScratchRegister);
ma_add(ScratchRegister, dest, SetCond);
}
void
MacroAssemblerARMCompat::and32(Imm32 imm, const Address &dest)
{
@ -1498,12 +1505,24 @@ MacroAssemblerARMCompat::or32(Imm32 imm, const Address &dest)
store32(ScratchRegister, dest);
}
void
MacroAssemblerARMCompat::xorPtr(Imm32 imm, Register dest)
{
ma_eor(imm, dest);
}
void
MacroAssemblerARMCompat::orPtr(Imm32 imm, Register dest)
{
ma_orr(imm, dest);
}
void
MacroAssemblerARMCompat::andPtr(Imm32 imm, Register dest)
{
ma_and(imm, dest);
}
void
MacroAssemblerARMCompat::move32(const Imm32 &imm, const Register &dest)
{
@ -1933,6 +1952,13 @@ MacroAssemblerARMCompat::subPtr(Imm32 imm, const Register dest)
ma_sub(imm, dest);
}
void
MacroAssemblerARMCompat::subPtr(const Address &addr, const Register dest)
{
loadPtr(addr, ScratchRegister);
ma_sub(ScratchRegister, dest);
}
void
MacroAssemblerARMCompat::addPtr(Imm32 imm, const Register dest)
{

4
js/src/ion/arm/MacroAssembler-arm.h
View File

@ -925,8 +925,11 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
void and32(Imm32 imm, Register dest);
void and32(Imm32 imm, const Address &dest);
void or32(Imm32 imm, const Address &dest);
void xorPtr(Imm32 imm, Register dest);
void orPtr(Imm32 imm, Register dest);
void andPtr(Imm32 imm, Register dest);
void addPtr(Register src, Register dest);
void addPtr(const Address &src, Register dest);
void move32(const Imm32 &imm, const Register &dest);
@ -1023,6 +1026,7 @@ class MacroAssemblerARMCompat : public MacroAssemblerARM
void cmpPtr(const Address &lhs, const ImmWord &rhs);
void subPtr(Imm32 imm, const Register dest);
void subPtr(const Address &addr, const Register dest);
void addPtr(Imm32 imm, const Register dest);
void addPtr(Imm32 imm, const Address &dest);
void addPtr(ImmWord imm, const Register dest) {

27
js/src/ion/x64/Assembler-x64.h
View File

@ -390,6 +390,18 @@ class Assembler : public AssemblerX86Shared
void addq(const Register &src, const Register &dest) {
masm.addq_rr(src.code(), dest.code());
}
void addq(const Operand &src, const Register &dest) {
switch (src.kind()) {
case Operand::REG:
masm.addq_rr(src.reg(), dest.code());
break;
case Operand::REG_DISP:
masm.addq_mr(src.disp(), src.base(), dest.code());
break;
default:
JS_NOT_REACHED("unexpected operand kind");
}
}
void subq(Imm32 imm, const Register &dest) {
masm.subq_ir(imm.value, dest.code());
@ -397,6 +409,18 @@ class Assembler : public AssemblerX86Shared
void subq(const Register &src, const Register &dest) {
masm.subq_rr(src.code(), dest.code());
}
void subq(const Operand &src, const Register &dest) {
switch (src.kind()) {
case Operand::REG:
masm.subq_rr(src.reg(), dest.code());
break;
case Operand::REG_DISP:
masm.subq_mr(src.disp(), src.base(), dest.code());
break;
default:
JS_NOT_REACHED("unexpected operand kind");
}
}
void shlq(Imm32 imm, const Register &dest) {
masm.shlq_i8r(imm.value, dest.code());
}
@ -424,6 +448,9 @@ class Assembler : public AssemblerX86Shared
void xorq(const Register &src, const Register &dest) {
masm.xorq_rr(src.code(), dest.code());
}
void xorq(Imm32 imm, const Register &dest) {
masm.xorq_ir(imm.value, dest.code());
}
void mov(ImmWord word, const Register &dest) {
movq(word, dest);

12
js/src/ion/x64/MacroAssembler-x64.h
View File

@ -399,12 +399,18 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
movq(imm, ScratchReg);
addq(ScratchReg, dest);
}
void addPtr(const Address &src, const Register &dest) {
addq(Operand(src), dest);
}
void subPtr(Imm32 imm, const Register &dest) {
subq(imm, dest);
}
void subPtr(const Register &src, const Register &dest) {
subq(src, dest);
}
void subPtr(const Address &addr, const Register &dest) {
subq(Operand(addr), dest);
}
// Specialization for AbsoluteAddress.
void branchPtr(Condition cond, const AbsoluteAddress &addr, const Register &ptr, Label *label) {
@ -491,9 +497,15 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared
void lshiftPtr(Imm32 imm, Register dest) {
shlq(imm, dest);
}
void xorPtr(Imm32 imm, Register dest) {
xorq(imm, dest);
}
void orPtr(Imm32 imm, Register dest) {
orq(imm, dest);
}
void andPtr(Imm32 imm, Register dest) {
andq(imm, dest);
}
void splitTag(Register src, Register dest) {
if (src != dest)

15
js/src/ion/x86/MacroAssembler-x86.h
View File

@ -386,9 +386,18 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
void addPtr(Imm32 imm, const Address &dest) {
addl(imm, Operand(dest));
}
void addPtr(const Address &src, const Register &dest) {
addl(Operand(src), dest);
}
void subPtr(Imm32 imm, const Register &dest) {
subl(imm, dest);
}
void subPtr(const Register &src, const Register &dest) {
subl(src, dest);
}
void subPtr(const Address &addr, const Register &dest) {
subl(Operand(addr), dest);
}
template <typename T, typename S>
void branchPtr(Condition cond, T lhs, S ptr, Label *label) {
@ -666,9 +675,15 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared
void lshiftPtr(Imm32 imm, Register dest) {
shll(imm, dest);
}
void xorPtr(Imm32 imm, Register dest) {
xorl(imm, dest);
}
void orPtr(Imm32 imm, Register dest) {
orl(imm, dest);
}
void andPtr(Imm32 imm, Register dest) {
andl(imm, dest);
}
void loadInstructionPointerAfterCall(const Register &dest) {
movl(Operand(StackPointer, 0x0), dest);