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https://gitlab.winehq.org/wine/wine-gecko.git
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Bug 476042 - Integrate sparc nanojit intro tracemonkey. r=gal, r=jim.
This commit is contained in:
Leon Sha<leon.sha@sun.com>
parent
ddb759753a
commit
128a82a274
@ -2502,6 +2502,10 @@ arm*-*)
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ENABLE_JIT=1
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NANOJIT_ARCH=ARM
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;;
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sparc*-*)
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ENABLE_JIT=1
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NANOJIT_ARCH=Sparc
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;;
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esac
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MOZ_ARG_DISABLE_BOOL(jit,
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@ -2521,6 +2525,9 @@ i?86-*)
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arm*-*)
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AC_DEFINE(AVMPLUS_ARM)
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;;
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sparc-*)
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AC_DEFINE(AVMPLUS_SPARC)
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;;
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esac
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case "$target_os" in
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@ -2122,7 +2122,11 @@ class RegExpNativeCompiler {
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LIns* compileFlatDoubleChar(jschar ch1, jschar ch2, LIns* pos,
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LInsList& fails)
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{
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#ifdef IS_BIG_ENDIAN
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uint32 word = (ch1 << 16) | ch2;
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#else
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uint32 word = (ch2 << 16) | ch1;
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#endif
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/*
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* Fast case-insensitive test for ASCII letters: convert text
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* char to lower case by bit-or-ing in 32 and compare.
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@ -49,6 +49,10 @@
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extern "C" void __clear_cache(char *BEG, char *END);
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#endif
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#ifdef AVMPLUS_SPARC
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extern "C" void sync_instruction_memory(caddr_t v, u_int len);
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#endif
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namespace nanojit
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{
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@ -932,6 +936,20 @@ namespace nanojit
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// to execute junk
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# if defined(UNDER_CE)
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FlushInstructionCache(GetCurrentProcess(), NULL, NULL);
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#elif defined AVMPLUS_SPARC
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// Clear Instruction Cache
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for (int i = 0; i < 2; i++) {
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Page *p = (i == 0) ? _nativePages : _nativeExitPages;
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Page *first = p;
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while (p) {
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if (!p->next || p->next != p+1) {
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sync_instruction_memory((char *)first, NJ_PAGE_SIZE);
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first = p->next;
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}
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p = p->next;
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}
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}
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# elif defined(AVMPLUS_UNIX)
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for (int i = 0; i < 2; i++) {
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Page *p = (i == 0) ? _nativePages : _nativeExitPages;
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@ -689,8 +689,13 @@ namespace nanojit
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return *(const uint64_t*)ptr;
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#else
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union { uint64_t tmp; int32_t dst[2]; } u;
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#ifdef AVMPLUS_BIG_ENDIAN
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u.dst[0] = l->v[1];
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u.dst[1] = l->v[0];
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#else
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u.dst[0] = l->v[0];
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u.dst[1] = l->v[1];
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#endif
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return u.tmp;
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#endif
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}
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@ -704,8 +709,13 @@ namespace nanojit
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return *(const double*)ptr;
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#else
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union { uint32_t dst[2]; double tmpf; } u;
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#ifdef AVMPLUS_BIG_ENDIAN
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u.dst[0] = l->v[1];
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u.dst[1] = l->v[0];
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#else
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u.dst[0] = l->v[0];
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u.dst[1] = l->v[1];
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#endif
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return u.tmpf;
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#endif
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}
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@ -51,6 +51,8 @@
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#endif
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#elif defined(NANOJIT_PPC)
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#include "NativePpc.h"
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#elif defined(NANOJIT_SPARC)
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#include "NativeSparc.h"
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#elif defined(NANOJIT_AMD64)
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#include "NativeAMD64.h"
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#else
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@ -115,7 +117,7 @@ namespace nanojit {
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#define gpn(r) regNames[(r)]
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#define fpn(r) regNames[(r)]
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#else
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#define asm_output(f, ...)
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#define asm_output(...)
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#define gpn(r)
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#define fpn(r)
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#endif /* NJ_VERBOSE */
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1127
js/src/nanojit/NativeSparc.cpp
Normal file
1127
js/src/nanojit/NativeSparc.cpp
Normal file
File diff suppressed because it is too large
Load Diff
936
js/src/nanojit/NativeSparc.h
Normal file
936
js/src/nanojit/NativeSparc.h
Normal file
@ -0,0 +1,936 @@
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/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: t; tab-width: 4 -*- */
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is [Open Source Virtual Machine].
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*
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* The Initial Developer of the Original Code is
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* Adobe System Incorporated.
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* Portions created by the Initial Developer are Copyright (C) 2004-2007
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Adobe AS3 Team
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* leon.sha@sun.com
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either the GNU General Public License Version 2 or later (the "GPL"), or
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* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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* in which case the provisions of the GPL or the LGPL are applicable instead
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* of those above. If you wish to allow use of your version of this file only
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* under the terms of either the GPL or the LGPL, and not to allow others to
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* use your version of this file under the terms of the MPL, indicate your
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* decision by deleting the provisions above and replace them with the notice
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* and other provisions required by the GPL or the LGPL. If you do not delete
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* the provisions above, a recipient may use your version of this file under
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* the terms of any one of the MPL, the GPL or the LGPL.
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef __nanojit_NativeSparc__
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#define __nanojit_NativeSparc__
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#define count_instr()
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#define count_ret()
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#define count_push()
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#define count_pop()
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#define count_st()
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#define count_stq()
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#define count_ld()
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#define count_ldq()
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#define count_call()
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#define count_calli()
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#define count_prolog()
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#define count_alu()
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#define count_mov()
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#define count_fpu()
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#define count_jmp()
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#define count_jcc()
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#define count_fpuld()
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#define count_aluld()
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#define count_alust()
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#define count_pushld()
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#define count_imt()
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namespace nanojit
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{
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#ifdef MMGC_SPARC
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const int NJ_LOG2_PAGE_SIZE = 12; // 4K
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#else
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const int NJ_LOG2_PAGE_SIZE = 13; // 8K
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#endif
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const int NJ_MAX_REGISTERS = 30; // L0 - L7, I0 - I5, F2 - F14
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const int NJ_STACK_OFFSET = 0;
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const int LARGEST_UNDERRUN_PROT = 32; // largest value passed to underrunProtect
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#define NJ_MAX_STACK_ENTRY 256
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#define NJ_MAX_PARAMETERS 1
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const int NJ_ALIGN_STACK = 16;
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typedef uint32_t NIns;
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// These are used as register numbers in various parts of the code
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typedef enum
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{
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G0 = 0,
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G1 = 1,
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G2 = 2,
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G3 = 3,
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G4 = 4,
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G5 = 5, // Reserved for system
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G6 = 6, // Reserved for system
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G7 = 7, // Reserved for system
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O0 = 8,
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O1 = 9,
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O2 = 10,
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O3 = 11,
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O4 = 12,
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O5 = 13,
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O6 = 14, // SP
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O7 = 15, // Not used.
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L0 = 16,
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L1 = 17,
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L2 = 18,
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L3 = 19,
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L4 = 20,
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L5 = 21,
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L6 = 22,
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L7 = 23,
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I0 = 24,
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I1 = 25,
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I2 = 26,
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I3 = 27,
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I4 = 28,
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I5 = 29,
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I6 = 30, // FP
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I7 = 31, // Not used
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SP = O6,
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FP = I6,
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F0 = 0,
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F1 = 1,
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F2 = 2,
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F3 = 3,
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F4 = 4,
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F5 = 5,
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F6 = 6,
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F7 = 7,
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F8 = 8,
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F9 = 9,
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F10 = 10,
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F11 = 11,
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F12 = 12,
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F13 = 13,
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F14 = 14,
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F15 = 15,
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F16 = 16,
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F17 = 17,
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F18 = 18,
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F19 = 19,
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F20 = 20,
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F21 = 21,
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F22 = 22,
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F23 = 23,
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F24 = 24,
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F25 = 25,
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F26 = 26,
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F27 = 27,
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F28 = 28,
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F29 = 29,
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F30 = 30,
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F31 = 31,
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// helpers
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FRAME_PTR = G4,
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FirstReg = 0,
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LastReg = 29,
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UnknownReg = 30
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}
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Register;
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// We only use 32 registers to be managed.
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// So we choose some of them.
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// And other unmanaged registers we can use them directly.
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// The registers that can be used directly are G0-G4, L0, L2, L4, L6
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// SP, FP, F8-F12, F24-F28
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typedef int RegisterMask;
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#define _rmask_(r) (1<<(r))
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static const int NumSavedRegs = 6;
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static const RegisterMask SavedRegs = 1<<L1 | 1<<L3 | 1<<L5 | 1<<L7 |
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1<<I0 | 1<<I1 | 1<<I2 | 1<<I3 |
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1<<I4 | 1<<I5;
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static const RegisterMask GpRegs = SavedRegs | 1<<O0 | 1<<O1 | 1<<O2 |
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1<<O3 | 1<<O4 | 1<<O5;
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static const RegisterMask FpRegs = 1<<F0 | 1<<F2 | 1<<F4 | 1<<F6 |
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1<<F14 | 1<<F16 | 1<<F18 | 1<<F20 |
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1<<F22;
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static const RegisterMask AllowableFlagRegs = GpRegs;
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#define nextreg(r) Register(r+1)
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#define prevreg(r) Register(r-1)
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verbose_only( extern const char* regNames[]; )
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#define DECLARE_PLATFORM_STATS()
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#define DECLARE_PLATFORM_REGALLOC()
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#define DECLARE_PLATFORM_ASSEMBLER() \
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const static Register argRegs[6], retRegs[1]; \
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bool has_cmov; \
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void nativePageReset(); \
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void nativePageSetup(); \
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void underrunProtect(int bytes); \
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void asm_align_code();
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#define swapptrs() { NIns* _tins = _nIns; _nIns=_nExitIns; _nExitIns=_tins; }
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#define IMM32(i) \
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--_nIns; \
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*((int32_t*)_nIns) = (int32_t)(i)
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#define CALL(c) do { \
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int offset = (c->_address) - ((int)_nIns) + 4; \
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int i = 0x40000000 | ((offset >> 2) & 0x3FFFFFFF); \
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IMM32(i); \
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verbose_only(asm_output("call %s",(c->_name));) \
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} while (0)
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#define Format_2_1(rd, op2, imm22) do { \
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int i = rd << 25 | op2 << 22 | (imm22 & 0x3FFFFF); \
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IMM32(i); \
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} while (0)
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#define Format_2_2(a, cond, op2, disp22) \
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Format_2_1((a & 0x1) << 4 | (cond & 0xF), op2, disp22)
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#define Format_2_3(a, cond, op2, cc1, cc0, p, disp19) \
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Format_2_2(a, cond, op2, (cc1 & 0x1) << 21 | (cc0 & 0x1) << 20 | (p & 0x1) << 19 | (disp19 & 0x7FFFF))
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#define Format_2_4(a, rcond, op2, d16hi, p, rs1, d16lo) \
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Format_2_2(a, (rcond & 0x7), op2, (d16hi & 0x3) << 20 | (p & 0x1) << 19 | rs1 << 14 | (d16lo & 0x3FFF))
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#define Format_3(op1, rd, op3, bits19) do { \
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int i = op1 << 30 | rd << 25 | op3 << 19 | (bits19 & 0x7FFFF); \
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IMM32(i); \
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} while (0)
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#define Format_3_1(op1, rd, op3, rs1, bit8, rs2) \
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Format_3(op1, rd, op3, rs1 << 14 | (bit8 & 0xFF) << 5 | rs2)
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#define Format_3_1I(op1, rd, op3, rs1, simm13) \
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Format_3(op1, rd, op3, rs1 << 14 | 1 << 13 | (simm13 & 0x1FFF))
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#define Format_3_2(op1, rd, op3, rs1, rcond, rs2) \
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Format_3(op1, rd, op3, rs1 << 14 | (rcond & 0x3) << 10 | rs2)
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#define Format_3_2I(op1, rd, op3, rs1, rcond, simm10) \
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Format_3(op1, rd, op3, rs1 << 14 | 1 << 13 | (rcond & 0x3) << 10 | (simm10 & 0x1FFF))
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#define Format_3_3(op1, rd, op3, rs1, cmask, mmask) \
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Format_3(op1, rd, op3, rs1 << 14 | 1 << 13 | (cmask & 0x7) << 5 | (mmask & 0xF))
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#define Format_3_4(op1, rd, op3, bits19) \
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Format_3(op1, rd, op3, bits19)
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#define Format_3_5(op1, rd, op3, rs1, x, rs2) \
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Format_3(op1, rd, op3, rs1 << 14 | (x & 0x1) << 12 | rs2)
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#define Format_3_6(op1, rd, op3, rs1, shcnt32) \
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Format_3(op1, rd, op3, rs1 << 14 | 1 << 13 | (shcnt32 & 0x3F))
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#define Format_3_7(op1, rd, op3, rs1, shcnt64) \
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Format_3(op1, rd, op3, rs1 << 14 | 1 << 13 | 1 << 12 | (shcnt64 & 0x7F))
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#define Format_3_8(op1, rd, op3, rs1, bits9, rs2) \
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Format_3(op1, rd, op3, rs1 << 14 | (bits9 & 0x1FF) << 5 | rs2)
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#define Format_3_9(op1, cc1, cc0, op3, rs1, bits9, rs2) \
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Format_3(op1, (cc1 & 0x1) << 1 | (cc0 & 0x1), op3, rs1 << 14 | (bits9 & 0x1FF) << 5 | rs2)
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#define Format_4_1(rd, op3, rs1, cc1, cc0, rs2) \
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Format_3(2, rd, op3, rs1 << 14 | (cc1 & 0x1) << 12 | (cc0 & 0x1) << 11 | rs2)
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#define Format_4_1I(rd, op3, rs1, cc1, cc0, simm11) \
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Format_3(2, rd, op3, rs1 << 14 | (cc1 & 0x1) << 12 | 1 << 13 |(cc0 & 0x1) << 11 | (simm11 & 0x7FF))
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#define Format_4_2(rd, op3, cc2, cond, cc1, cc0, rs2) \
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Format_3(2, rd, op3, (cc2 & 0x1) << 18 | (cond & 0xF) << 14 | (cc1 & 0x1) << 12 | (cc0 & 0x1) << 11 | rs2)
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#define Format_4_2I(rd, op3, cc2, cond, cc1, cc0, simm11) \
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Format_3(2, rd, op3, (cc2 & 0x1) << 18 | (cond & 0xF) << 14 | 1 << 13 | (cc1 & 0x1) << 12 | (cc0 & 0x1) << 11 | (simm11 & 0x7FF))
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#define Format_4_3(rd, op3, rs1, cc1, cc0, swap_trap) \
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Format_3(2, rd, op3, rs1 << 14 | 1 << 13 | (cc1 & 0x1) << 12 | (cc0 & 0x1) << 11 | (swap_trap & 0x7F))
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#define Format_4_4(rd, op3, rs1, rcond, opf_low, rs2) \
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Format_3(2, rd, op3, rs1 << 14 | (rcond & 0x7) << 10 | (opf_low & 0x1F) << 5 | rs2)
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#define Format_4_5(rd, op3, cond, opf_cc, opf_low, rs2) \
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Format_3(2, rd, op3, (cond & 0xF) << 14 | (opf_cc & 0x7) << 11 | (opf_low & 0x3F) << 5 | rs2)
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#define ADD(rs1, rs2, rd) \
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do { \
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asm_output("add %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
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Format_3_1(2, rd, 0, rs1, 0, rs2); \
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} while (0)
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#define AND(rs1, rs2, rd) \
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do { \
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asm_output("and %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
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Format_3_1(2, rd, 0x1, rs1, 0, rs2); \
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} while (0)
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||||
#define BA(a, dsp22) \
|
||||
do { \
|
||||
asm_output("ba %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x8, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("be %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x1, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BG(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bg %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xA, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BGU(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bgu %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xC, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BGE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bge %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xB, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BL(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bl %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x3, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BLE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("ble %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x2, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BLEU(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bleu %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x4, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BCC(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bcc %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xd, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BCS(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bcs %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x5, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BVC(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bvc %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xf, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BVS(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bvc %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x7, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define BNE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("bne %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x9, 0x2, dsp22); \
|
||||
} while (0)
|
||||
|
||||
#define FABSS(rs2, rd) \
|
||||
do { \
|
||||
asm_output("fabs %s, %s", gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, 0, 0x9, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FADDD(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("faddd %s, %s, %s", gpn(rs1+32), gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, rs1, 0x42, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FBE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fbe %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x9, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBNE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fbne %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x1, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBUE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fbue %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xA, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBG(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fng %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x6, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBUG(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fbug %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x5, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBGE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fbge %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xB, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBUGE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fbuge %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xC, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBL(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fbl %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0x4, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FBLE(a, dsp22) \
|
||||
do { \
|
||||
asm_output("fble %p", _nIns + dsp22 - 1); \
|
||||
Format_2_2(a, 0xD, 0x6, dsp22); \
|
||||
} while(0)
|
||||
|
||||
#define FCMPD(rs1, rs2) \
|
||||
do { \
|
||||
asm_output("fcmpd %s, %s", gpn(rs1+32), gpn(rs2+32)); \
|
||||
Format_3_9(2, 0, 0, 0x35, rs1, 0x52, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FSUBD(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("fsubd %s, %s, %s", gpn(rs1+32), gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, rs1, 0x46, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FMULD(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("fmuld %s, %s, %s", gpn(rs1+32), gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, rs1, 0x4a, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FDIVD(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("fdivd %s, %s, %s", gpn(rs1+32), gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, rs1, 0x4e, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FMOVD(rs2, rd) \
|
||||
do { \
|
||||
asm_output("fmovd %s, %s", gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, 0, 0x2, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FNEGD(rs2, rd) \
|
||||
do { \
|
||||
asm_output("fnegd %s, %s", gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, 0, 0x6, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define FITOD(rs2, rd) \
|
||||
do { \
|
||||
asm_output("fitod %s, %s", gpn(rs2+32), gpn(rd+32)); \
|
||||
Format_3_8(2, rd, 0x34, 0, 0xc8, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define JMPL(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("jmpl [%s + %s]", gpn(rs1), gpn(rs2)); \
|
||||
Format_3_1(2, rd, 0x38, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define JMPLI(rs1, simm13, rd) \
|
||||
do { \
|
||||
asm_output("jmpl [%s + %d]", gpn(rs1), simm13); \
|
||||
Format_3_1I(2, rd, 0x38, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define LDF(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %s], %s", gpn(rs1), gpn(rs2), gpn(rd+32)); \
|
||||
Format_3_1(3, rd, 0x20, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define LDFI(rs1, simm13, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %d], %s", gpn(rs1), simm13, gpn(rd+32)); \
|
||||
Format_3_1I(3, rd, 0x20, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define LDSB(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %s], %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(3, rd, 0x9, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define LDSBI(rs1, simm13, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %d], %s", gpn(rs1), simm13, gpn(rd)); \
|
||||
Format_3_1I(3, rd, 0x9, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define LDSH(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %s], %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(3, rd, 0xa, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define LDSHI(rs1, simm13, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %d], %s", gpn(rs1), simm13, gpn(rd)); \
|
||||
Format_3_1I(3, rd, 0xa, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define LDSW(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %s], %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(3, rd, 0x8, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define LDSWI(rs1, simm13, rd) \
|
||||
do { \
|
||||
asm_output("ld [%s + %d], %s", gpn(rs1), simm13, gpn(rd)); \
|
||||
Format_3_1I(3, rd, 0x8, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define MOVE(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("move %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 1, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVNE(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movne %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 9, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVL(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movl %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 3, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVLE(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movle %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 2, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVG(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movg %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 0xa, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVGE(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movge %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 0xb, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVCS(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movcs %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 5, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVLEU(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movleu %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 4, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVGU(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movgu %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 0xc, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVCC(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movcc %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 0xd, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVVC(rs, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movvc %s, %s", gpn(rs), gpn(rd)); \
|
||||
Format_4_2(rd, 0x2c, cc2, 0xf, cc1, cc0, rs); \
|
||||
} while (0)
|
||||
|
||||
#define MOVEI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("move %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 1, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVFEI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("move %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 9, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVNEI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("move %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 9, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVLI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("move %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 3, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVFLI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("move %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 4, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVLEI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movle %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 2, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVFLEI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movle %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 0xd, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVGI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movg %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 0xa, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVFGI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movg %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 6, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVGEI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movge %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 0xb, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVFGEI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movge %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 0xb, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVCSI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movcs %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 5, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVLEUI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movleu %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 4, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVGUI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movgu %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 0xc, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVCCI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movcc %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 0xd, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MOVVSI(simm11, cc2, cc1, cc0, rd) \
|
||||
do { \
|
||||
asm_output("movvs %d, %s", simm11, gpn(rd)); \
|
||||
Format_4_2I(rd, 0x2c, cc2, 7, cc1, cc0, simm11); \
|
||||
} while (0)
|
||||
|
||||
#define MULX(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("mul %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x9, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define NOP() \
|
||||
do { \
|
||||
asm_output("nop"); \
|
||||
Format_2_1(0, 0x4, 0); \
|
||||
} while (0)
|
||||
|
||||
#define ORI(rs1, simm13, rd) \
|
||||
do { \
|
||||
asm_output("or %s, %d, %s", gpn(rs1), simm13, gpn(rd)); \
|
||||
Format_3_1I(2, rd, 0x2, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define OR(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("or %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x2, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define ORN(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("orn %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x6, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define ANDCC(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("andcc %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x11, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define RESTORE(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("restore"); \
|
||||
Format_3_1(2, rd, 0x3D, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define SAVEI(rs1, simm13, rd) \
|
||||
do { \
|
||||
asm_output("save %s, %d, %s", gpn(rs1), simm13, gpn(rd)); \
|
||||
Format_3_1I(2, rd, 0x3C, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define SAVE(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("save %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x3C, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define SETHI(imm22, rd) \
|
||||
do { \
|
||||
asm_output("sethi %p, %s", imm22, gpn(rd)); \
|
||||
Format_2_1(rd, 0x4, (imm22 >> 10)); \
|
||||
} while (0)
|
||||
|
||||
#define SLL(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("sll %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_5(2, rd, 0x25, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define SRA(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("sra %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_5(2, rd, 0x27, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define SRL(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("srl %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_5(2, rd, 0x26, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define STF(rd, rs1, rs2) \
|
||||
do { \
|
||||
asm_output("st %s, [%s + %s]", gpn(rd+32), gpn(rs1), gpn(rs2)); \
|
||||
Format_3_1(3, rd, 0x24, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define STFI(rd, simm13, rs1) \
|
||||
do { \
|
||||
asm_output("st %s, [%s + %d]", gpn(rd+32), gpn(rs1), simm13); \
|
||||
Format_3_1I(3, rd, 0x24, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define STW(rd, rs2, rs1) \
|
||||
do { \
|
||||
asm_output("st %s, [%s + %s]", gpn(rd), gpn(rs1), gpn(rs2)); \
|
||||
Format_3_1(3, rd, 0x4, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define STWI(rd, simm13, rs1) \
|
||||
do { \
|
||||
asm_output("st %s, [%s + %d]", gpn(rd), gpn(rs1), simm13); \
|
||||
Format_3_1I(3, rd, 0x4, rs1, simm13); \
|
||||
} while (0)
|
||||
|
||||
#define SUBCC(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("subcc %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x14, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define SUB(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("sub %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x4, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
#define XOR(rs1, rs2, rd) \
|
||||
do { \
|
||||
asm_output("xor %s, %s, %s", gpn(rs1), gpn(rs2), gpn(rd)); \
|
||||
Format_3_1(2, rd, 0x3, rs1, 0, rs2); \
|
||||
} while (0)
|
||||
|
||||
// Returns true if imm below 13-bit unsigned immediate)
|
||||
#define isIMM13(imm) \
|
||||
(imm) <= 4095 && (imm) >= -4096
|
||||
|
||||
#define isIMM19(imm) \
|
||||
(imm) <= 0x3ffff && (imm) >= -0x40000
|
||||
|
||||
#define isIMM22(imm) \
|
||||
(imm) <= 0x1fffff && (imm) >= -0x200000
|
||||
|
||||
#define SET32(imm32, rd) \
|
||||
if(isIMM13(imm32)) { \
|
||||
ORI(G0, imm32, rd); \
|
||||
} else { \
|
||||
ORI(rd, imm32 & 0x3FF, rd); \
|
||||
SETHI(imm32, rd); \
|
||||
}
|
||||
|
||||
#define STDF32(rd, imm32, rs1) \
|
||||
if(isIMM13(imm32+4)) { \
|
||||
STFI(rd+1, imm32+4, rs1); \
|
||||
STFI(rd, imm32, rs1); \
|
||||
} else { \
|
||||
STF(rd+1, L0, rs1); \
|
||||
SET32(imm32+4, L0); \
|
||||
STF(rd, L0, rs1); \
|
||||
SET32(imm32, L0); \
|
||||
}
|
||||
|
||||
#define LDDF32(rs1, imm32, rd) \
|
||||
if(isIMM13(imm32+4)) { \
|
||||
LDFI(rs1, imm32+4, rd+1); \
|
||||
LDFI(rs1, imm32, rd); \
|
||||
} else { \
|
||||
LDF(rs1, L0, rd+1); \
|
||||
SET32(imm32+4, L0); \
|
||||
LDF(rs1, L0, rd); \
|
||||
SET32(imm32, L0); \
|
||||
}
|
||||
|
||||
#define STW32(rd, imm32, rs1) \
|
||||
if(isIMM13(imm32)) { \
|
||||
STWI(rd, imm32, rs1); \
|
||||
} else { \
|
||||
STW(rd, L0, rs1); \
|
||||
SET32(imm32, L0); \
|
||||
}
|
||||
|
||||
#define LDSB32(rs1, imm32, rd) \
|
||||
if(isIMM13(imm32)) { \
|
||||
LDSBI(rs1, imm32, rd); \
|
||||
} else { \
|
||||
LDSB(rs1, L0, rd); \
|
||||
SET32(imm32, L0); \
|
||||
}
|
||||
|
||||
#define LDSH32(rs1, imm32, rd) \
|
||||
if(isIMM13(imm32)) { \
|
||||
LDSHI(rs1, imm32, rd); \
|
||||
} else { \
|
||||
LDSH(rs1, L0, rd); \
|
||||
SET32(imm32, L0); \
|
||||
}
|
||||
|
||||
#define LDSW32(rs1, imm32, rd) \
|
||||
if(isIMM13(imm32)) { \
|
||||
LDSWI(rs1, imm32, rd); \
|
||||
} else { \
|
||||
LDSW(rs1, L0, rd); \
|
||||
SET32(imm32, L0); \
|
||||
}
|
||||
|
||||
|
||||
// general Assemble
|
||||
#define JMP_long_nocheck(t) do { NOP(); JMPL(G0, G2, G0); ORI(G2, t & 0x3FF, G2); SETHI(t, G2); } while(0)
|
||||
#define JMP_long(t) do { underrunProtect(16); JMP_long_nocheck(t); } while(0)
|
||||
#define JMP_long_placeholder() JMP_long(0)
|
||||
|
||||
#define JCC(t, tt) \
|
||||
underrunProtect(32); \
|
||||
tt = ((intptr_t)t - (intptr_t)_nIns + 8) >> 2; \
|
||||
if( !(isIMM22((int32_t)tt)) ) { \
|
||||
NOP(); \
|
||||
JMPL(G0, G2, G0); \
|
||||
SET32((intptr_t)t, G2); \
|
||||
NOP(); \
|
||||
BA(0, 5); \
|
||||
tt = 4; \
|
||||
} \
|
||||
NOP()
|
||||
|
||||
#define JMP(t) do { \
|
||||
if (!t) { \
|
||||
JMP_long_placeholder(); \
|
||||
} else { \
|
||||
intptr_t tt; \
|
||||
JCC(t, tt); \
|
||||
BA(0, tt); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
#define MR(d, s) do { underrunProtect(4); ORI(s, 0, d); } while(0)
|
||||
|
||||
}
|
||||
#endif // __nanojit_NativeSparc__
|
||||
@ -46,6 +46,14 @@
|
||||
|
||||
#include "jstypes.h"
|
||||
|
||||
#if !defined(AVMPLUS_LITTLE_ENDIAN) && !defined(AVMPLUS_BIG_ENDIAN)
|
||||
#ifdef IS_BIG_ENDIAN
|
||||
#define AVMPLUS_BIG_ENDIAN
|
||||
#else
|
||||
#define AVMPLUS_LITTLE_ENDIAN
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define FASTCALL JS_FASTCALL
|
||||
|
||||
#if defined(JS_NO_FASTCALL)
|
||||
|
||||
@ -50,6 +50,8 @@
|
||||
#define NANOJIT_ARM
|
||||
#elif AVMPLUS_PPC
|
||||
#define NANOJIT_PPC
|
||||
#elif AVMPLUS_SPARC
|
||||
#define NANOJIT_SPARC
|
||||
#elif AVMPLUS_AMD64
|
||||
#define NANOJIT_AMD64
|
||||
#define NANOJIT_64BIT
|
||||
|
||||
Loading…
Reference in New Issue
Block a user