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Bug 965242 - ARM simulator: Fix the decoding of the VCVT instructions fraction bits. r=nbp

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This commit is contained in:
Douglas Crosher 2014-01-29 10:47:37 +11:00
parent c0cd3833c6
commit 06f29d293e
1 changed files with 1 additions and 1 deletions
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2
js/src/jit/arm/Simulator-arm.cpp
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@ -3119,7 +3119,7 @@ Simulator::decodeTypeVFP(SimInstruction *instr)
} else if ((instr->opc2Value() == 0xA) && (instr->opc3Value() == 0x3) &&
(instr->bit(8) == 1)) {
// vcvt.f64.s32 Dd, Dd, #<fbits>
int fraction_bits = 32 - ((instr->bit(5) << 4) | instr->bits(3, 0));
int fraction_bits = 32 - ((instr->bits(3, 0) << 1) | instr->bit(5));
int fixed_value = get_sinteger_from_s_register(vd * 2);
double divide = 1 << fraction_bits;
set_d_register_from_double(vd, fixed_value / divide);