2008-06-30 15:33:41 -07:00
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/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: t; tab-width: 4 -*- */
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2008-06-18 20:57:17 -07:00
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is [Open Source Virtual Machine].
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*
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* The Initial Developer of the Original Code is
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* Adobe System Incorporated.
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* Portions created by the Initial Developer are Copyright (C) 2004-2007
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Adobe AS3 Team
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either the GNU General Public License Version 2 or later (the "GPL"), or
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* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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* in which case the provisions of the GPL or the LGPL are applicable instead
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* of those above. If you wish to allow use of your version of this file only
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* under the terms of either the GPL or the LGPL, and not to allow others to
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* use your version of this file under the terms of the MPL, indicate your
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* decision by deleting the provisions above and replace them with the notice
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* and other provisions required by the GPL or the LGPL. If you do not delete
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* the provisions above, a recipient may use your version of this file under
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* the terms of any one of the MPL, the GPL or the LGPL.
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*
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* ***** END LICENSE BLOCK ***** */
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#ifndef __nanojit_NativeArm__
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#define __nanojit_NativeArm__
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namespace nanojit
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{
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const int NJ_LOG2_PAGE_SIZE = 12; // 4K
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#define NJ_MAX_REGISTERS 11
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#define NJ_MAX_STACK_ENTRY 256
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#define NJ_MAX_PARAMETERS 16
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#define NJ_ALIGN_STACK 8
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#define NJ_STACK_OFFSET 8
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#define NJ_SOFTFLOAT
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#define NJ_STACK_GROWTH_UP
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#define NJ_CONSTANT_POOLS
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const int NJ_MAX_CPOOL_OFFSET = 4096;
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const int NJ_CPOOL_SIZE = 16;
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typedef int NIns;
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/* ARM registers */
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typedef enum
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{
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R0 = 0,
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R1 = 1,
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R2 = 2,
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R3 = 3,
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R4 = 4,
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R5 = 5,
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R6 = 6,
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R7 = 7,
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R8 = 8,
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R9 = 9,
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R10 = 10,
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//FP =11,
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IP = 12,
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SP = 13,
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LR = 14,
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PC = 15,
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FP = 13,
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// Pseudo-register for floating point
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F0 = 0,
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// helpers
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FRAME_PTR = 11,
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ESP = 13,
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FirstReg = 0,
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LastReg = 10,
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Scratch = 12,
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UnknownReg = 11
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}
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Register;
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/* ARM condition codes */
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typedef enum
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{
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EQ = 0x0, // Equal
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NE = 0x1, // Not Equal
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CS = 0x2, // Carry Set (or HS)
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CC = 0x3, // Carry Clear (or LO)
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MI = 0x4, // MInus
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PL = 0x5, // PLus
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VS = 0x6, // oVerflow Set
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VC = 0x7, // oVerflow Clear
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HI = 0x8, // HIgher
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LS = 0x9, // Lower or Same
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GE = 0xA, // Greater or Equal
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LT = 0xB, // Less Than
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GT = 0xC, // Greater Than
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LE = 0xD, // Less or Equal
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AL = 0xE, // ALways
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NV = 0xF // NeVer
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}
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ConditionCode;
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typedef int RegisterMask;
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typedef struct _FragInfo
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{
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RegisterMask needRestoring;
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NIns* epilogue;
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}
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FragInfo;
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static const RegisterMask SavedRegs = 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10;
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static const RegisterMask FpRegs = 0x0000; // FST0-FST7
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static const RegisterMask GpRegs = 0x07FF;
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static const RegisterMask AllowableFlagRegs = 1<<R0 | 1<<R1 | 1<<R2 | 1<<R3 | 1<<R4 | 1<<R5 | 1<<R6 | 1<<R7 | 1<<R8 | 1<<R9 | 1<<R10;
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#define firstreg() R0
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#define nextreg(r) (Register)((int)r+1)
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#define imm2register(c) (Register)(c-1)
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verbose_only( extern const char* regNames[]; )
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// abstract to platform specific calls
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#define nExtractPlatformFlags(x) 0
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#define DECLARE_PLATFORM_STATS() \
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counter_define(x87Top);
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#define DECLARE_PLATFORM_REGALLOC()
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#define DECLARE_PLATFORM_ASSEMBLER()\
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const static Register argRegs[4], retRegs[2];\
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void LD32_nochk(Register r, int32_t imm);\
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2008-09-02 22:29:23 -07:00
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void BL(NIns*);\
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void BL_far(NIns*);\
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2008-07-16 14:21:31 -07:00
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void CALL(const CallInfo*);\
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2008-06-18 20:57:17 -07:00
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void underrunProtect(int bytes);\
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bool has_cmov;\
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void nativePageReset();\
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void nativePageSetup();\
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2008-09-02 22:29:23 -07:00
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void flushCache(NIns*,NIns*);\
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2008-06-18 20:57:17 -07:00
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int* _nSlot;\
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int* _nExitSlot;
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2008-07-16 14:21:31 -07:00
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#define asm_farg(i) NanoAssert(false)
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2008-06-18 20:57:17 -07:00
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//printf("jmp_l_n count=%d, nins=%X, %X = %X\n", (_c), nins, _nIns, ((intptr_t)(nins+(_c))-(intptr_t)_nIns - 4) );
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#define swapptrs() { NIns* _tins = _nIns; _nIns=_nExitIns; _nExitIns=_tins; \
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int* _nslot = _nSlot;\
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_nSlot = _nExitSlot;\
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_nExitSlot = _nslot;}
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#define IMM32(imm) *(--_nIns) = (NIns)((imm));
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#define FUNCADDR(addr) ( ((int)addr) )
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#define OP_IMM (1<<25)
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#define COND_AL (0xE<<28)
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typedef enum
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{
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LSL_imm = 0, // LSL #c - Logical Shift Left
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LSL_reg = 1, // LSL Rc - Logical Shift Left
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LSR_imm = 2, // LSR #c - Logical Shift Right
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LSR_reg = 3, // LSR Rc - Logical Shift Right
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ASR_imm = 4, // ASR #c - Arithmetic Shift Right
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ASR_reg = 5, // ASR Rc - Arithmetic Shift Right
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ROR_imm = 6, // Rotate Right (c != 0)
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RRX = 6, // Rotate Right one bit with extend (c == 0)
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ROR_reg = 7 // Rotate Right
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}
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ShiftOperator;
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#define LD32_size 4
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#define BEGIN_NATIVE_CODE(x) \
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{ DWORD* _nIns = (uint8_t*)x
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#define END_NATIVE_CODE(x) \
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(x) = (dictwordp*)_nIns; }
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// BX
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#define BX(_r) do {\
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underrunProtect(4);\
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*(--_nIns) = (NIns)( COND_AL | (0x12<<20) | (0xFFF<<8) | (1<<4) | (_r));\
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asm_output("bx LR"); } while(0)
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// _l = _r OR _l
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#define OR(_l,_r) do {\
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underrunProtect(4);\
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*(--_nIns) = (NIns)( COND_AL | (0xC<<21) | (_r<<16) | (_l<<12) | (_l) );\
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asm_output2("or %s,%s",gpn(_l),gpn(_r)); } while(0)
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// _r = _r OR _imm
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#define ORi(_r,_imm) do {\
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NanoAssert(isU8((_imm)));\
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underrunProtect(4); \
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | (0xC<<21) | (_r<<16) | (_r<<12) | ((_imm)&0xFF) );\
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asm_output2("or %s,%d",gpn(_r), (_imm)); } while(0)
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// _l = _r AND _l
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#define AND(_l,_r) do {\
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underrunProtect(4);\
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*(--_nIns) = (NIns)( COND_AL | ((_r)<<16) | ((_l)<<12) | (_l));\
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asm_output2("and %s,%s",gpn(_l),gpn(_r)); } while(0)
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// _r = _r AND _imm
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#define ANDi(_r,_imm) do {\
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if (isU8((_imm))) {\
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underrunProtect(4);\
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | ((_r)<<16) | ((_r)<<12) | ((_imm)&0xFF) );\
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asm_output2("and %s,%d",gpn(_r),(_imm));}\
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else if ((_imm)<0 && (_imm)>-256) {\
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2008-09-02 22:29:23 -07:00
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underrunProtect(8);\
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2008-06-18 20:57:17 -07:00
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*(--_nIns) = (NIns)( COND_AL | ((_r)<<16) | ((_r)<<12) | (Scratch) );\
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asm_output2("and %s,%s",gpn(_r),gpn(Scratch));\
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*(--_nIns) = (NIns)( COND_AL | (0x3E<<20) | ((Scratch)<<12) | (((_imm)^0xFFFFFFFF)&0xFF) );\
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asm_output2("mvn %s,%d",gpn(Scratch),(_imm));}\
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else NanoAssert(0);\
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} while (0)
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// _l = _l XOR _r
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#define XOR(_l,_r) do {\
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underrunProtect(4);\
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*(--_nIns) = (NIns)( COND_AL | (1<<21) | ((_r)<<16) | ((_l)<<12) | (_l));\
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asm_output2("eor %s,%s",gpn(_l),gpn(_r)); } while(0)
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// _r = _r XOR _imm
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#define XORi(_r,_imm) do { \
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NanoAssert(isU8((_imm)));\
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underrunProtect(4); \
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<21) | ((_r)<<16) | ((_r)<<12) | ((_imm)&0xFF) );\
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asm_output2("eor %s,%d",gpn(_r),(_imm)); } while(0)
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// _l = _l + _r
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#define ADD(_l,_r) do {\
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underrunProtect(4);\
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*(--_nIns) = (NIns)( COND_AL | (1<<23) | ((_r)<<16) | ((_l)<<12) | (_l));\
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asm_output2("add %s,%s",gpn(_l),gpn(_r)); } while(0)
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// _r = _r + _imm
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#define ADDi(_r,_imm) do {\
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if ((_imm)>-256 && (_imm)<256) {\
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underrunProtect(4);\
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if ((_imm)>=0) *(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_r)<<16) | ((_r)<<12) | ((_imm)&0xFF) );\
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else *(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<22) | ((_r)<<16) | ((_r)<<12) | ((-(_imm))&0xFF) );}\
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else {\
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if ((_imm)>=0){\
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if ((_imm)<=1020 && (((_imm)&3)==0) ){\
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underrunProtect(4);\
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_r)<<16) | ((_r)<<12) | (15<<8)| ((_imm)>>2) );}\
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else {\
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underrunProtect(4+LD32_size);\
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*(--_nIns) = (NIns)( COND_AL | (1<<23) | ((_r)<<16) | ((_r)<<12) | (Scratch));\
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LD32_nochk(Scratch, _imm);}}\
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else{\
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if ((_imm)>=-510){\
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underrunProtect(8);\
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int rem = -(_imm) - 255;\
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<22) | ((_r)<<16) | ((_r)<<12) | ((rem)&0xFF) );\
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<22) | ((_r)<<16) | ((_r)<<12) | (0xFF) );}\
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else {\
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underrunProtect(4+LD32_size);\
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*(--_nIns) = (NIns)( COND_AL | (1<<22) | ((_r)<<16) | ((_r)<<12) | (Scratch));\
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LD32_nochk(Scratch, -(_imm));}\
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}\
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}\
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asm_output2("addi %s,%d",gpn(_r),(_imm));} while(0)
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// _l = _l - _r
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#define SUB(_l,_r) do {\
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underrunProtect(4); \
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*(--_nIns) = (NIns)( COND_AL | (1<<22) | ((_l)<<16) | ((_l)<<12) | (_r));\
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asm_output2("sub %s,%s",gpn(_l),gpn(_r)); } while(0)
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// _r = _r - _imm
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#define SUBi(_r,_imm) do{\
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if ((_imm)>-256 && (_imm)<256){\
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underrunProtect(4);\
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if ((_imm)>=0) *(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<22) | ((_r)<<16) | ((_r)<<12) | ((_imm)&0xFF) );\
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else *(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_r)<<16) | ((_r)<<12) | ((-(_imm))&0xFF) );}\
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else {\
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if ((_imm)>=0){\
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if ((_imm)<=510){\
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underrunProtect(8);\
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int rem = (_imm) - 255;\
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NanoAssert(rem<256);\
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<22) | ((_r)<<16) | ((_r)<<12) | (rem&0xFF) );\
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*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<22) | ((_r)<<16) | ((_r)<<12) | (0xFF) );}\
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else {\
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underrunProtect(4+LD32_size);\
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*(--_nIns) = (NIns)( COND_AL | (1<<22) | ((_r)<<16) | ((_r)<<12) | (Scratch));\
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LD32_nochk(Scratch, _imm);}}\
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else{\
|
|
|
|
if ((_imm)>=-510) {\
|
|
|
|
underrunProtect(8);\
|
|
|
|
int rem = -(_imm) - 255;\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_r)<<16) | ((_r)<<12) | ((rem)&0xFF) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_r)<<16) | ((_r)<<12) | (0xFF) );}\
|
|
|
|
else {\
|
|
|
|
underrunProtect(4+LD32_size);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (1<<23) | ((_r)<<16) | ((_r)<<12) | (Scratch));\
|
|
|
|
LD32_nochk(Scratch, -(_imm));}\
|
|
|
|
}\
|
|
|
|
}\
|
|
|
|
asm_output2("sub %s,%d",gpn(_r),(_imm));} while (0)
|
|
|
|
|
|
|
|
// _l = _l * _r
|
|
|
|
#define MUL(_l,_r) do {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (_l)<<16 | (_l)<<8 | 0x90 | (_r) );\
|
|
|
|
asm_output2("mul %s,%s",gpn(_l),gpn(_r)); } while(0)
|
|
|
|
|
|
|
|
|
|
|
|
// RSBS
|
|
|
|
// _r = -_r
|
|
|
|
#define NEG(_r) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x27<<20) | ((_r)<<16) | ((_r)<<12) ); \
|
|
|
|
asm_output1("neg %s",gpn(_r)); } while(0)
|
|
|
|
|
|
|
|
// MVNS
|
|
|
|
// _r = !_r
|
|
|
|
#define NOT(_r) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1F<<20) | ((_r)<<12) | (_r) ); \
|
|
|
|
asm_output1("mvn %s",gpn(_r)); } while(0)
|
|
|
|
|
|
|
|
// MOVS _r, _r, LSR <_s>
|
|
|
|
// _r = _r >> _s
|
|
|
|
#define SHR(_r,_s) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1B<<20) | ((_r)<<12) | ((_s)<<8) | (LSR_reg<<4) | (_r) ); \
|
|
|
|
asm_output2("shr %s,%s",gpn(_r),gpn(_s)); } while(0)
|
|
|
|
|
|
|
|
// MOVS _r, _r, LSR #_imm
|
|
|
|
// _r = _r >> _imm
|
|
|
|
#define SHRi(_r,_imm) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1B<<20) | ((_r)<<12) | ((_imm)<<7) | (LSR_imm<<4) | (_r) ); \
|
|
|
|
asm_output2("shr %s,%d",gpn(_r),_imm); } while(0)
|
|
|
|
|
|
|
|
// MOVS _r, _r, ASR <_s>
|
|
|
|
// _r = _r >> _s
|
|
|
|
#define SAR(_r,_s) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1B<<20) | ((_r)<<12) | ((_s)<<8) | (ASR_reg<<4) | (_r) ); \
|
|
|
|
asm_output2("asr %s,%s",gpn(_r),gpn(_s)); } while(0)
|
|
|
|
|
|
|
|
|
|
|
|
// MOVS _r, _r, ASR #_imm
|
|
|
|
// _r = _r >> _imm
|
|
|
|
#define SARi(_r,_imm) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1B<<20) | ((_r)<<12) | ((_imm)<<7) | (ASR_imm<<4) | (_r) ); \
|
|
|
|
asm_output2("asr %s,%d",gpn(_r),_imm); } while(0)
|
|
|
|
|
|
|
|
// MOVS _r, _r, LSL <_s>
|
|
|
|
// _r = _r << _s
|
|
|
|
#define SHL(_r,_s) do {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1B<<20) | ((_r)<<12) | ((_s)<<8) | (LSL_reg<<4) | (_r) ); \
|
|
|
|
asm_output2("lsl %s,%s",gpn(_r),gpn(_s)); } while(0)
|
|
|
|
|
|
|
|
// MOVS _r, _r, LSL #_imm
|
|
|
|
// _r = _r << _imm
|
|
|
|
#define SHLi(_r,_imm) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1B<<20) | ((_r)<<12) | ((_imm)<<7) | (LSL_imm<<4) | (_r) ); \
|
|
|
|
asm_output2("lsl %s,%d",gpn(_r),(_imm)); } while(0)
|
|
|
|
|
|
|
|
// TST
|
|
|
|
#define TEST(_d,_s) do{\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x11<<20) | ((_d)<<16) | (_s) ); \
|
|
|
|
asm_output2("test %s,%s",gpn(_d),gpn(_s));} while(0)
|
|
|
|
|
|
|
|
// CMP
|
|
|
|
#define CMP(_l,_r) do{\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x015<<20) | ((_l)<<16) | (_r) ); \
|
|
|
|
asm_output2("cmp %s,%s",gpn(_l),gpn(_r));} while(0)
|
|
|
|
|
|
|
|
// CMP (or CMN)
|
|
|
|
#define CMPi(_r,_imm) do{\
|
|
|
|
if (_imm<0) { \
|
|
|
|
if ((_imm)>-256) {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x37<<20) | ((_r)<<16) | (-(_imm)) );}\
|
|
|
|
else {\
|
|
|
|
underrunProtect(4+LD32_size);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x17<<20) | ((_r)<<16) | (Scratch) ); \
|
|
|
|
LD32_nochk(Scratch, (_imm));}\
|
|
|
|
} else {\
|
|
|
|
if ((_imm)<256){\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x035<<20) | ((_r)<<16) | ((_imm)&0xFF) ); \
|
|
|
|
} else {\
|
|
|
|
underrunProtect(4+LD32_size);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x015<<20) | ((_r)<<16) | (Scratch) ); \
|
|
|
|
LD32_nochk(Scratch, (_imm));\
|
|
|
|
}\
|
|
|
|
}\
|
|
|
|
asm_output2("cmp %s,%X",gpn(_r),(_imm)); } while(0)
|
|
|
|
|
|
|
|
// MOV
|
|
|
|
#define MR(_d,_s) do {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0xD<<21) | ((_d)<<12) | (_s) );\
|
|
|
|
asm_output2("mov %s,%s",gpn(_d),gpn(_s)); } while (0)
|
|
|
|
|
|
|
|
|
|
|
|
#define MR_cond(_d,_s,_cond,_nm) do {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( ((_cond)<<28) | (0xD<<21) | ((_d)<<12) | (_s) );\
|
|
|
|
asm_output2(_nm " %s,%s",gpn(_d),gpn(_s)); } while (0)
|
|
|
|
|
|
|
|
#define MREQ(dr,sr) MR_cond(dr, sr, EQ, "moveq")
|
|
|
|
#define MRNE(dr,sr) MR_cond(dr, sr, NE, "movne")
|
|
|
|
#define MRL(dr,sr) MR_cond(dr, sr, LT, "movlt")
|
|
|
|
#define MRLE(dr,sr) MR_cond(dr, sr, LE, "movle")
|
|
|
|
#define MRG(dr,sr) MR_cond(dr, sr, GT, "movgt")
|
|
|
|
#define MRGE(dr,sr) MR_cond(dr, sr, GE, "movge")
|
|
|
|
#define MRB(dr,sr) MR_cond(dr, sr, CC, "movcc")
|
|
|
|
#define MRBE(dr,sr) MR_cond(dr, sr, LS, "movls")
|
|
|
|
#define MRA(dr,sr) MR_cond(dr, sr, HI, "movcs")
|
|
|
|
#define MRAE(dr,sr) MR_cond(dr, sr, CS, "movhi")
|
2008-07-07 02:47:40 -07:00
|
|
|
#define MRNO(dr,sr) MR_cond(dr, sr, VC, "movvc") // overflow clear
|
|
|
|
#define MRNC(dr,sr) MR_cond(dr, sr, CC, "movcc") // carry clear
|
2008-06-18 20:57:17 -07:00
|
|
|
|
|
|
|
#define LD(_d,_off,_b) do{\
|
|
|
|
if ((_off)<0){\
|
|
|
|
underrunProtect(4);\
|
|
|
|
NanoAssert((_off)>-4096);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x51<<20) | ((_b)<<16) | ((_d)<<12) | ((-(_off))&0xFFF) );\
|
|
|
|
} else {\
|
|
|
|
if (isS16(_off) || isU16(_off)) {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
NanoAssert((_off)<4096);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x59<<20) | ((_b)<<16) | ((_d)<<12) | ((_off)&0xFFF) );}\
|
|
|
|
else {\
|
|
|
|
underrunProtect(4+LD32_size);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x79<<20) | ((_b)<<16) | ((_d)<<12) | Scratch );\
|
|
|
|
LD32_nochk(Scratch, _off);}\
|
|
|
|
} asm_output3("ld %s,%d(%s)",gpn((_d)),(_off),gpn((_b))); }while(0)
|
|
|
|
|
|
|
|
|
|
|
|
#define LDi(_d,_imm) do {\
|
|
|
|
if (isS8((_imm)) || isU8((_imm))) { \
|
|
|
|
underrunProtect(4); \
|
|
|
|
if ((_imm)<0) *(--_nIns) = (NIns)( COND_AL | (0x3E<<20) | ((_d)<<12) | (((_imm)^0xFFFFFFFF)&0xFF) );\
|
|
|
|
else *(--_nIns) = (NIns)( COND_AL | (0x3B<<20) | ((_d)<<12) | ((_imm)&0xFF) );\
|
|
|
|
} else {\
|
|
|
|
underrunProtect(LD32_size);\
|
|
|
|
LD32_nochk(_d, (_imm));\
|
|
|
|
} asm_output2("ld %s,%d",gpn((_d)),(_imm)); } while(0)
|
|
|
|
|
|
|
|
|
|
|
|
// load 8-bit, zero extend (aka LDRB)
|
|
|
|
// note, only 5-bit offsets (!) are supported for this, but that's all we need at the moment
|
|
|
|
// (LDRB actually allows 12-bit offset in ARM mode but constraining to 5-bit gives us advantage for Thumb)
|
|
|
|
// @todo, untested!
|
|
|
|
#define LD8Z(_d,_off,_b) do{ \
|
|
|
|
NanoAssert((d)>=0&&(d)<=31);\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x5D<<20) | ((_b)<<16) | ((_d)<<12) | ((_off)&0xfff) );\
|
|
|
|
asm_output3("ldrb %s,%d(%s)", gpn(_d),(_off),gpn(_b));\
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
#define ST(_b,_off,_r) do{\
|
|
|
|
underrunProtect(4); \
|
|
|
|
if ((_off)<0) *(--_nIns) = (NIns)( COND_AL | (0x50<<20) | ((_b)<<16) | ((_r)<<12) | ((-(_off))&0xFFF) );\
|
|
|
|
else *(--_nIns) = (NIns)( COND_AL | (0x58<<20) | ((_b)<<16) | ((_r)<<12) | ((_off)&0xFFF) );\
|
|
|
|
asm_output3("str %s, %d(%s)",gpn(_r), (_off),gpn(_b)); } while(0)
|
|
|
|
|
|
|
|
|
|
|
|
#define STi(_b,_off,_imm) do{\
|
|
|
|
NanoAssert((_off)>0);\
|
|
|
|
if (isS8((_imm)) || isU8((_imm))) { \
|
|
|
|
underrunProtect(8); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x58<<20) | ((_b)<<16) | ((Scratch)<<12) | ((_off)&0xFFF) );\
|
|
|
|
asm_output3("str %s, %d(%s)",gpn(Scratch), (_off),gpn(_b)); \
|
|
|
|
if ((_imm)<0) *(--_nIns) = (NIns)( COND_AL | (0x3E<<20) | (Scratch<<12) | (((_imm)^0xFFFFFFFF)&0xFF) );\
|
|
|
|
else *(--_nIns) = (NIns)( COND_AL | (0x3B<<20) | (Scratch<<12) | ((_imm)&0xFF) );\
|
|
|
|
asm_output2("ld %s,%d",gpn((Scratch)),(_imm)); }\
|
|
|
|
else {\
|
|
|
|
underrunProtect(4+LD32_size);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x58<<20) | ((_b)<<16) | ((Scratch)<<12) | ((_off)&0xFFF) );\
|
|
|
|
asm_output3("str %s, %d(%s)",gpn(Scratch), (_off),gpn(_b)); \
|
|
|
|
LD32_nochk(Scratch, (_imm));}\
|
|
|
|
} while(0);
|
|
|
|
|
|
|
|
|
|
|
|
#define LEA(_r,_d,_b) do{ \
|
|
|
|
NanoAssert((_d)<=1020); \
|
|
|
|
NanoAssert(((_d)&3)==0); \
|
|
|
|
if (_b!=SP) NanoAssert(0); \
|
|
|
|
if ((_d)<256) { \
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x28<<20) | ((_b)<<16) | ((_r)<<12) | ((_d)&0xFF) );}\
|
|
|
|
else{ \
|
|
|
|
underrunProtect(8); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x4<<21) | ((_b)<<16) | ((_r)<<12) | (2<<7)| (_r) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x3B<<20) | ((_r)<<12) | (((_d)>>2)&0xFF) );}\
|
|
|
|
asm_output2("lea %s, %d(SP)", gpn(_r), _d); \
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
|
|
|
|
//#define RET() underrunProtect(1); *(--_nIns) = 0xc3; asm_output("ret")
|
|
|
|
//#define NOP() underrunProtect(1); *(--_nIns) = 0x90; asm_output("nop")
|
|
|
|
//#define INT3() underrunProtect(1); *(--_nIns) = 0xcc; asm_output("int3")
|
|
|
|
//#define RET() INT3()
|
|
|
|
|
2008-09-02 22:29:23 -07:00
|
|
|
#define BKPT_nochk() do { *(--_nIns) = (NIns)( (0xE<<24) | (0x12<<20) | (0x7<<4) ); } while (0);
|
2008-06-18 20:57:17 -07:00
|
|
|
|
|
|
|
// this is pushing a reg
|
|
|
|
#define PUSHr(_r) do {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x92<<20) | (SP<<16) | (1<<(_r)) ); \
|
|
|
|
asm_output1("push %s",gpn(_r)); } while (0)
|
|
|
|
|
|
|
|
// STMDB
|
|
|
|
#define PUSH_mask(_mask) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x92<<20) | (SP<<16) | (_mask) ); \
|
|
|
|
asm_output1("push %x", (_mask));} while (0)
|
|
|
|
|
|
|
|
// this form of PUSH takes a base + offset
|
|
|
|
// we need to load into scratch reg, then push onto stack
|
|
|
|
#define PUSHm(_off,_b) do {\
|
|
|
|
NanoAssert( (int)(_off)>0 );\
|
|
|
|
underrunProtect(8);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x92<<20) | (SP<<16) | (1<<(Scratch)) ); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x59<<20) | ((_b)<<16) | ((Scratch)<<12) | ((_off)&0xFFF) );\
|
|
|
|
asm_output2("push %d(%s)",(_off),gpn(_b)); } while (0)
|
|
|
|
|
2008-07-07 02:47:40 -07:00
|
|
|
#define POPr(_r) do {\
|
2008-06-18 20:57:17 -07:00
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x8B<<20) | (SP<<16) | (1<<(_r)) );\
|
|
|
|
asm_output1("pop %s",gpn(_r));} while (0)
|
|
|
|
|
|
|
|
#define POP_mask(_mask) do {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x8B<<20) | (SP<<16) | (_mask) );\
|
|
|
|
asm_output1("pop %x", (_mask));} while (0)
|
|
|
|
|
2008-09-02 22:29:23 -07:00
|
|
|
#define PC_OFFSET_FROM(target,frompc) ((intptr_t)(target) - ((intptr_t)(frompc) + 8))
|
|
|
|
#define JMP_S24_OFFSET_OK(offs) ((-(1<<24)) <= (offs) && (offs) < (1<<24))
|
|
|
|
|
|
|
|
// (XXX This ought to be a function instead of a macro)
|
|
|
|
//
|
|
|
|
// Branch to target address _t with condition _c, doing underrun
|
|
|
|
// checks (_chk == 1) or skipping them (_chk == 0).
|
|
|
|
//
|
|
|
|
// If the jump fits in a relative jump (+/-32MB), emit that.
|
|
|
|
// If the jump is unconditional, emit the dest address inline in
|
|
|
|
// the instruction stream and load it into pc.
|
|
|
|
// If the jump has a condition, but noone's mucked with _nIns and our _nSlot
|
|
|
|
// pointer is valid, stick the constant in the slot and emit a conditional
|
|
|
|
// load into pc.
|
|
|
|
// Otherwise, emit the conditional load into pc from a nearby constant,
|
|
|
|
// and emit a jump to jump over it it in case the condition fails.
|
|
|
|
//
|
|
|
|
// NB: JMP_nochk depends on this not calling samepage() when _c == AL
|
|
|
|
#define B_cond_chk(_c,_t,_chk) do { \
|
|
|
|
int32 offs = PC_OFFSET_FROM(_t,(intptr_t)(_nIns)-4); \
|
|
|
|
if (JMP_S24_OFFSET_OK(offs)) { \
|
|
|
|
if(_chk) underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( ((_c)<<28) | (0xA<<24) | (((offs)>>2) & 0xFFFFFF) ); \
|
|
|
|
} else if (_c == AL) { \
|
|
|
|
if(_chk) underrunProtect(8); \
|
|
|
|
*(--_nIns) = (NIns)(_t); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x51<<20) | (PC<<16) | (PC<<12) | 0x4 ); \
|
|
|
|
} else if (samepage(_nIns,_nSlot)) { \
|
|
|
|
if(_chk) underrunProtect(8); \
|
|
|
|
*(++_nSlot) = (NIns)(_t); \
|
|
|
|
offs = PC_OFFSET_FROM(_nSlot,(intptr_t)(_nIns)-4); \
|
|
|
|
NanoAssert(offs < 0); \
|
|
|
|
*(--_nIns) = (NIns)( ((_c)<<28) | (0x51<<20) | (PC<<16) | (PC<<12) | ((-offs) & 0xFFFFFF) ); \
|
|
|
|
} else { \
|
|
|
|
if(_chk) underrunProtect(24); \
|
|
|
|
*(--_nIns) = (NIns)(_t); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0xA<<24) | ((-4)>>2) & 0xFFFFFF ); \
|
|
|
|
*(--_nIns) = (NIns)( ((_c)<<28) | (0x51<<20) | (PC<<16) | (PC<<12) | 0x0 ); \
|
|
|
|
} \
|
|
|
|
asm_output2("%s %p\n", _c == AL ? "jmp" : "b(cnd)", (void*)(_t)); \
|
|
|
|
} while(0)
|
2008-06-18 20:57:17 -07:00
|
|
|
|
2008-09-02 22:29:23 -07:00
|
|
|
#define B_cond(_c,_t) \
|
|
|
|
B_cond_chk(_c,_t,1)
|
2008-06-18 20:57:17 -07:00
|
|
|
|
2008-09-02 22:29:23 -07:00
|
|
|
// NB: don't use COND_AL here, we shift the condition into place!
|
|
|
|
#define JMP(_t) \
|
|
|
|
B_cond_chk(AL,_t,1)
|
2008-06-18 20:57:17 -07:00
|
|
|
|
2008-09-02 22:29:23 -07:00
|
|
|
#define JMP_nochk(_t) \
|
|
|
|
B_cond_chk(AL,_t,0)
|
2008-07-15 13:06:05 -07:00
|
|
|
|
2008-09-02 22:29:23 -07:00
|
|
|
// emit a placeholder that will be filled in later by nPatchBranch;
|
|
|
|
// emit two breakpoint instructions in case something goes wrong with
|
|
|
|
// the patching.
|
|
|
|
#define JMP_long_placeholder() do { \
|
|
|
|
underrunProtect(8); \
|
|
|
|
BKPT_nochk(); \
|
|
|
|
BKPT_nochk(); \
|
|
|
|
} while(0)
|
2008-07-15 13:06:05 -07:00
|
|
|
|
|
|
|
#define JA(t) do {B_cond(HI,t); asm_output1("ja 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNA(t) do {B_cond(LS,t); asm_output1("jna 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JB(t) do {B_cond(CC,t); asm_output1("jb 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNB(t) do {B_cond(CS,t); asm_output1("jnb 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JE(t) do {B_cond(EQ,t); asm_output1("je 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNE(t) do {B_cond(NE,t); asm_output1("jne 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JBE(t) do {B_cond(LS,t); asm_output1("jbe 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNBE(t) do {B_cond(HI,t); asm_output1("jnbe 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JAE(t) do {B_cond(CS,t); asm_output1("jae 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNAE(t) do {B_cond(CC,t); asm_output1("jnae 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JL(t) do {B_cond(LT,t); asm_output1("jl 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNL(t) do {B_cond(GE,t); asm_output1("jnl 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JLE(t) do {B_cond(LE,t); asm_output1("jle 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNLE(t) do {B_cond(GT,t); asm_output1("jnle 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JGE(t) do {B_cond(GE,t); asm_output1("jge 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNGE(t) do {B_cond(LT,t); asm_output1("jnge 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JG(t) do {B_cond(GT,t); asm_output1("jg 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNG(t) do {B_cond(LE,t); asm_output1("jng 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JC(t) do {B_cond(CS,t); asm_output1("bcs 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNC(t) do {B_cond(CC,t); asm_output1("bcc 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JO(t) do {B_cond(VS,t); asm_output1("bvs 0x%08x",(unsigned int)t); } while(0)
|
|
|
|
#define JNO(t) do {B_cond(VC,t); asm_output1("bvc 0x%08x",(unsigned int)t); } while(0)
|
2008-06-18 20:57:17 -07:00
|
|
|
|
|
|
|
// used for testing result of an FP compare
|
|
|
|
// JP = comparison false
|
|
|
|
#define JP(t) do {B_cond(EQ,NE,t); asm_output1("jp 0x%08x",t); } while(0)
|
|
|
|
|
|
|
|
// JNP = comparison true
|
|
|
|
#define JNP(t) do {B_cond(NE,EQ,t); asm_output1("jnp 0x%08x",t); } while(0)
|
|
|
|
|
|
|
|
|
|
|
|
// floating point
|
|
|
|
#define FNSTSW_AX() do {NanoAssert(0); asm_output("fnstsw_ax"); } while(0)
|
|
|
|
#define FFREE(r) do {NanoAssert(0); asm_output1("ffree %s",gpn(b)); } while(0)
|
|
|
|
#define FSTQ(p,d,b) do {NanoAssert(0); asm_output2("fstq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FSTPQ(d,b) FSTQ(1,d,b)
|
|
|
|
//#define FSTPQ(d,b) do {NanoAssert(0); asm_output2("fstpq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FCOM(p,d,b) do {NanoAssert(0); asm_output2("fcom %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FCOMP(d,b) do {NanoAssert(0); asm_output2("fcomp %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FLDQ(d,b) do {NanoAssert(0); asm_output2("fldq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FILDQ(d,b) do {NanoAssert(0); asm_output2("fildq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FILD(d,b) do {NanoAssert(0); asm_output2("fild %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FADD(d,b) do {NanoAssert(0); asm_output2("faddq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FSUB(d,b) do {NanoAssert(0); asm_output2("fsubq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FSUBR(d,b) do {NanoAssert(0); asm_output2("fsubr %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FMUL(d,b) do {NanoAssert(0); asm_output2("fmulq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FDIV(d,b) do {NanoAssert(0); asm_output2("fdivq %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FDIVR(d,b) do {NanoAssert(0); asm_output2("fdivr %d(%s)",d,gpn(b)); } while(0)
|
|
|
|
#define FSTP(r) do {NanoAssert(0); asm_output1("fst st(%d)",r); } while(0)
|
|
|
|
#define FLD1() do {NanoAssert(0); asm_output("fld1"); } while(0)
|
|
|
|
#define FLDZ() do {NanoAssert(0); asm_output("fldz"); } while(0)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// MOV(EQ) _r, #1
|
|
|
|
// EOR(NE) _r, _r
|
|
|
|
#define SET(_r,_cond,_opp)\
|
|
|
|
underrunProtect(8); \
|
|
|
|
*(--_nIns) = (NIns)( (_opp<<28) | (1<<21) | ((_r)<<16) | ((_r)<<12) | (_r) );\
|
|
|
|
*(--_nIns) = (NIns)( (_cond<<28) | (0x3A<<20) | ((_r)<<12) | (1) );
|
|
|
|
|
|
|
|
|
|
|
|
#define SETE(r) do {SET(r,EQ,NE); asm_output1("sete %s",gpn(r)); } while(0)
|
|
|
|
#define SETL(r) do {SET(r,LT,GE); asm_output1("setl %s",gpn(r)); } while(0)
|
|
|
|
#define SETLE(r) do {SET(r,LE,GT); asm_output1("setle %s",gpn(r)); } while(0)
|
|
|
|
#define SETG(r) do {SET(r,GT,LE); asm_output1("setg %s",gpn(r)); } while(0)
|
|
|
|
#define SETGE(r) do {SET(r,GE,LT); asm_output1("setge %s",gpn(r)); } while(0)
|
|
|
|
#define SETB(r) do {SET(r,CC,CS); asm_output1("setb %s",gpn(r)); } while(0)
|
|
|
|
#define SETBE(r) do {SET(r,LS,HI); asm_output1("setb %s",gpn(r)); } while(0)
|
|
|
|
#define SETAE(r) do {SET(r,CS,CC); asm_output1("setae %s",gpn(r)); } while(0)
|
|
|
|
#define SETA(r) do {SET(r,HI,LS); asm_output1("seta %s",gpn(r)); } while(0)
|
2008-07-07 02:47:40 -07:00
|
|
|
#define SETO(r) do {SET(r,VS,LS); asm_output1("seto %s",gpn(r)); } while(0)
|
|
|
|
#define SETC(r) do {SET(r,CS,LS); asm_output1("setc %s",gpn(r)); } while(0)
|
2008-06-18 20:57:17 -07:00
|
|
|
|
|
|
|
// This zero-extends a reg that has been set using one of the SET macros,
|
|
|
|
// but is a NOOP on ARM/Thumb
|
|
|
|
#define MOVZX8(r,r2)
|
|
|
|
|
|
|
|
// Load and sign extend a 16-bit value into a reg
|
|
|
|
#define MOVSX(_d,_off,_b) do{\
|
|
|
|
if ((_off)>=0){\
|
|
|
|
if ((_off)<256){\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1D<<20) | ((_b)<<16) | ((_d)<<12) | ((((_off)>>4)&0xF)<<8) | (0xF<<4) | ((_off)&0xF) );}\
|
|
|
|
else if ((_off)<=510) {\
|
|
|
|
underrunProtect(8);\
|
|
|
|
int rem = (_off) - 255;\
|
|
|
|
NanoAssert(rem<256);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1D<<20) | ((_d)<<16) | ((_d)<<12) | ((((rem)>>4)&0xF)<<8) | (0xF<<4) | ((rem)&0xF) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_b)<<16) | ((_d)<<12) | (0xFF) );}\
|
|
|
|
else {\
|
|
|
|
underrunProtect(16);\
|
|
|
|
int rem = (_off) & 3;\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x19<<20) | ((_b)<<16) | ((_d)<<12) | (0xF<<4) | (_d) );\
|
|
|
|
asm_output3("ldrsh %s,[%s, #%d]",gpn(_d), gpn(_b), (_off));\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_d)<<16) | ((_d)<<12) | rem );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1A<<20) | ((_d)<<12) | (2<<7)| (_d) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x3B<<20) | ((_d)<<12) | (((_off)>>2)&0xFF) );\
|
|
|
|
asm_output2("mov %s,%d",gpn(_d),(_off));}}\
|
|
|
|
else {\
|
|
|
|
if ((_off)>-256) {\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x15<<20) | ((_b)<<16) | ((_d)<<12) | ((((-(_off))>>4)&0xF)<<8) | (0xF<<4) | ((-(_off))&0xF) );\
|
|
|
|
asm_output3("ldrsh %s,[%s, #%d]",gpn(_d), gpn(_b), (_off));}\
|
|
|
|
else if ((_off)>=-510){\
|
|
|
|
underrunProtect(8);\
|
|
|
|
int rem = -(_off) - 255;\
|
|
|
|
NanoAssert(rem<256);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x15<<20) | ((_d)<<16) | ((_d)<<12) | ((((rem)>>4)&0xF)<<8) | (0xF<<4) | ((rem)&0xF) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<22) | ((_b)<<16) | ((_d)<<12) | (0xFF) );}\
|
|
|
|
else NanoAssert(0);\
|
|
|
|
}\
|
|
|
|
} while(0)
|
|
|
|
|
|
|
|
#define STMIA(_b, _mask) do {\
|
|
|
|
underrunProtect(2);\
|
|
|
|
NanoAssert(((_mask)&rmask(_b))==0 && isU8(_mask));\
|
|
|
|
*(--_nIns) = (NIns)(COND_AL | (0x8A<<20) | ((_b)<<16) | (_mask)&0xFF);\
|
|
|
|
asm_output2("stmia %s!,{%x}", gpn(_b), _mask);} while (0)
|
|
|
|
|
|
|
|
#define LDMIA(_b, _mask) do {\
|
|
|
|
underrunProtect(2);\
|
|
|
|
NanoAssert(((_mask)&rmask(_b))==0 && isU8(_mask));\
|
|
|
|
*(--_nIns) = (NIns)(COND_AL | (0x8B<<20) | ((_b)<<16) | (_mask)&0xFF);\
|
|
|
|
asm_output2("ldmia %s!,{%x}", gpn(_b), (_mask));} while (0)
|
|
|
|
|
|
|
|
/*
|
|
|
|
#define MOVSX(_d,_off,_b) do{\
|
|
|
|
if ((_b)==SP){\
|
|
|
|
NanoAssert( (_off)>=0 );\
|
|
|
|
if ((_off)<256){\
|
|
|
|
underrunProtect(4);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1D<<20) | ((_b)<<16) | ((_d)<<12) | ((((_off)>>4)&0xF)<<8) | (0xF<<4) | ((_off)&0xF) );}\
|
|
|
|
else if ((_off)<=510) {\
|
|
|
|
underrunProtect(8);\
|
|
|
|
int rem = (_off) - 255;\
|
|
|
|
NanoAssert(rem<256);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1D<<20) | ((_d)<<16) | ((_d)<<12) | ((((rem)>>4)&0xF)<<8) | (0xF<<4) | ((rem)&0xF) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_b)<<16) | ((_d)<<12) | (0xFF) );}\
|
|
|
|
else {\
|
|
|
|
underrunProtect(16);\
|
|
|
|
int rem = (_off) & 3;\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x19<<20) | ((_b)<<16) | ((_d)<<12) | (0xF<<4) | (_d) );\
|
|
|
|
asm_output3("ldrsh %s,[%s, #%d]",gpn(_d), gpn(_b), (_off));\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_d)<<16) | ((_d)<<12) | rem );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1A<<20) | ((_d)<<12) | (2<<7)| (_d) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x3B<<20) | ((_d)<<12) | (((_off)>>2)&0xFF) );\
|
|
|
|
asm_output2("mov %s,%d",gpn(_d),(_off));}}\
|
|
|
|
else {\
|
|
|
|
if ((_off)>=0){\
|
|
|
|
if ((_off)<256) {\
|
|
|
|
underrunProtect(4); \
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1D<<20) | ((_b)<<16) | ((_d)<<12) | ((((_off)>>4)&0xF)<<8) | (0xF<<4) | ((_off)&0xF) );\
|
|
|
|
asm_output3("ldrsh %s,[%s, #%d]",gpn(_d), gpn(_b), (_off));}\
|
|
|
|
else if ((_off)<=510) {\
|
|
|
|
underrunProtect(8);\
|
|
|
|
int rem = (_off) - 255;\
|
|
|
|
NanoAssert(rem<256);\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x1D<<20) | ((_d)<<16) | ((_d)<<12) | ((((rem)>>4)&0xF)<<8) | (0xF<<4) | ((rem)&0xF) );\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | ((_b)<<16) | ((_d)<<12) | (0xFF) );}\
|
|
|
|
else NanoAssert(0);}\
|
|
|
|
else {\
|
|
|
|
if ((_off)>-256) {\
|
|
|
|
*(--_nIns) = (NIns)( COND_AL | (0x15<<20) | ((_b)<<16) | ((_d)<<12) | ((((-(_off))>>4)&0xF)<<8) | (0xF<<4) | ((-(_off))&0xF) );\
|
|
|
|
asm_output3("ldrsh %s,[%s, #%d]",gpn(_d), gpn(_b), (_off));}\
|
|
|
|
else {}}\
|
|
|
|
} while(0)
|
|
|
|
*/
|
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}
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#endif // __nanojit_NativeThumb__
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