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574 lines
16 KiB
C++
574 lines
16 KiB
C++
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/* -*- Mode: C++; c-basic-offset: 4; indent-tabs-mode: t; tab-width: 4 -*- */
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/* ***** BEGIN LICENSE BLOCK *****
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* Version: MPL 1.1/GPL 2.0/LGPL 2.1
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*
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* The contents of this file are subject to the Mozilla Public License Version
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* 1.1 (the "License"); you may not use this file except in compliance with
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* the License. You may obtain a copy of the License at
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* http://www.mozilla.org/MPL/
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*
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* Software distributed under the License is distributed on an "AS IS" basis,
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* WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License
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* for the specific language governing rights and limitations under the
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* License.
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*
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* The Original Code is [Open Source Virtual Machine].
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*
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* The Initial Developer of the Original Code is
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* Adobe System Incorporated.
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* Portions created by the Initial Developer are Copyright (C) 2004-2007
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* the Initial Developer. All Rights Reserved.
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*
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* Contributor(s):
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* Adobe AS3 Team
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*
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* Alternatively, the contents of this file may be used under the terms of
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* either the GNU General Public License Version 2 or later (the "GPL"), or
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* the GNU Lesser General Public License Version 2.1 or later (the "LGPL"),
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* in which case the provisions of the GPL or the LGPL are applicable instead
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* of those above. If you wish to allow use of your version of this file only
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* under the terms of either the GPL or the LGPL, and not to allow others to
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* use your version of this file under the terms of the MPL, indicate your
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* decision by deleting the provisions above and replace them with the notice
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* and other provisions required by the GPL or the LGPL. If you do not delete
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* the provisions above, a recipient may use your version of this file under
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* the terms of any one of the MPL, the GPL or the LGPL.
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*
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* ***** END LICENSE BLOCK ***** */
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#include "nanojit.h"
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#ifdef AVMPLUS_PORTING_API
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#include "portapi_nanojit.h"
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#endif
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#ifdef UNDER_CE
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#include <cmnintrin.h>
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#endif
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#if defined(AVMPLUS_LINUX)
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#include <asm/unistd.h>
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#endif
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namespace nanojit
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{
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#ifdef FEATURE_NANOJIT
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#ifdef NJ_VERBOSE
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const char* regNames[] = {"r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","IP","SP","LR","PC"};
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#endif
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const Register Assembler::argRegs[] = { R0, R1, R2, R3 };
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const Register Assembler::retRegs[] = { R0, R1 };
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void Assembler::nInit(AvmCore*)
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{
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// all ARMs have conditional move
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has_cmov = true;
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}
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NIns* Assembler::genPrologue(RegisterMask needSaving)
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{
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/**
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* Prologue
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*/
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// NJ_RESV_OFFSET is space at the top of the stack for us
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// to use for parameter passing (8 bytes at the moment)
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uint32_t stackNeeded = 4 * _activation.highwatermark + NJ_STACK_OFFSET;
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uint32_t savingCount = 0;
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uint32_t savingMask = 0;
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savingCount = 9; //R4-R10,R11,LR
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savingMask = SavedRegs | rmask(FRAME_PTR);
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(void)needSaving;
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// so for alignment purposes we've pushed return addr, fp, and savingCount registers
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uint32_t stackPushed = 4 * (2+savingCount);
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uint32_t aligned = alignUp(stackNeeded + stackPushed, NJ_ALIGN_STACK);
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int32_t amt = aligned - stackPushed;
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// Make room on stack for what we are doing
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if (amt)
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{
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SUBi(SP, amt);
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}
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verbose_only( verbose_outputf(" %p:",_nIns); )
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verbose_only( verbose_output(" patch entry"); )
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NIns *patchEntry = _nIns;
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MR(FRAME_PTR, SP);
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PUSH_mask(savingMask|rmask(LR));
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return patchEntry;
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}
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void Assembler::nFragExit(LInsp guard)
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{
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SideExit* exit = guard->exit();
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Fragment *frag = exit->target;
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GuardRecord *lr;
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if (frag && frag->fragEntry)
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{
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JMP(frag->fragEntry);
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lr = 0;
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}
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else
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{
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// target doesn't exit yet. emit jump to epilog, and set up to patch later.
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lr = placeGuardRecord(guard);
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// we need to know that there's an extra immediate value available
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// for us; always force a far jump here.
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BL_far(_epilogue);
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lr->jmp = _nIns;
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}
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// pop the stack frame first
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MR(SP, FRAME_PTR);
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#ifdef NJ_VERBOSE
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if (_frago->core()->config.show_stats) {
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// load R1 with Fragment *fromFrag, target fragment
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// will make use of this when calling fragenter().
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int fromfrag = int((Fragment*)_thisfrag);
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LDi(argRegs[1], fromfrag);
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}
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#endif
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// return value is GuardRecord*
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LDi(R2, int(lr));
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}
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NIns* Assembler::genEpilogue(RegisterMask restore)
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{
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BX(LR); // return
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MR(R0,R2); // return LinkRecord*
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RegisterMask savingMask = restore | rmask(FRAME_PTR) | rmask(LR);
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POP_mask(savingMask); // regs
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return _nIns;
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}
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void Assembler::asm_call(LInsp ins)
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{
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const CallInfo* call = callInfoFor(ins->fid());
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uint32_t atypes = call->_argtypes;
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uint32_t roffset = 0;
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// we need to detect if we have arg0 as LO followed by arg1 as F;
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// in that case, we need to skip using r1 -- the F needs to be
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// loaded in r2/r3, at least according to the ARM EABI and gcc 4.2's
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// generated code.
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bool arg0IsInt32FollowedByFloat = false;
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while ((atypes & 3) != ARGSIZE_NONE) {
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if (((atypes >> 4) & 3) == ARGSIZE_LO &&
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((atypes >> 2) & 3) == ARGSIZE_F &&
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((atypes >> 6) & 3) == ARGSIZE_NONE)
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{
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arg0IsInt32FollowedByFloat = true;
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break;
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}
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atypes >>= 2;
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}
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CALL(call);
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ArgSize sizes[10];
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uint32_t argc = call->get_sizes(sizes);
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for(uint32_t i=0; i < argc; i++)
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{
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uint32_t j = argc - i - 1;
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ArgSize sz = sizes[j];
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NanoAssert(sz == ARGSIZE_LO || sz == ARGSIZE_Q);
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// pre-assign registers R0-R3 for arguments (if they fit)
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Register r = (i+roffset) < 4 ? argRegs[i+roffset] : UnknownReg;
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asm_arg(sz, ins->arg(j), r);
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if (i == 0 && arg0IsInt32FollowedByFloat)
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roffset = 1;
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}
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}
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void Assembler::nMarkExecute(Page* page, int32_t count, bool enable)
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{
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#ifdef UNDER_CE
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DWORD dwOld;
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VirtualProtect(page, NJ_PAGE_SIZE, PAGE_EXECUTE_READWRITE, &dwOld);
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#endif
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#ifdef AVMPLUS_PORTING_API
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NanoJIT_PortAPI_MarkExecutable(page, (void*)((int32_t)page+count));
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#endif
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(void)page;
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(void)count;
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(void)enable;
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}
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Register Assembler::nRegisterAllocFromSet(int set)
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{
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// Note: The clz instruction only works on armv5 and up.
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#ifndef UNDER_CE
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#ifdef __ARMCC__
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register int i;
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__asm { clz i,set }
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Register r = Register(31-i);
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_allocator.free &= ~rmask(r);
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return r;
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#else
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// need to implement faster way
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int i=0;
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while (!(set & rmask((Register)i)))
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i ++;
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_allocator.free &= ~rmask((Register)i);
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return (Register) i;
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#endif
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#else
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Register r;
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r = (Register)_CountLeadingZeros(set);
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r = (Register)(31-r);
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_allocator.free &= ~rmask(r);
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return r;
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#endif
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}
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void Assembler::nRegisterResetAll(RegAlloc& a)
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{
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// add scratch registers to our free list for the allocator
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a.clear();
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a.used = 0;
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a.free = rmask(R0) | rmask(R1) | rmask(R2) | rmask(R3) | rmask(R4) | rmask(R5);
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debug_only(a.managed = a.free);
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}
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void Assembler::nPatchBranch(NIns* branch, NIns* target)
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{
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// Patch the jump in a loop
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// This is ALWAYS going to be a long branch (using the BL instruction)
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// Which is really 2 instructions, so we need to modify both
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// XXX -- this is B, not BL, at least on non-Thumb..
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// branch+2 because PC is always 2 instructions ahead on ARM/Thumb
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int32_t offset = int(target) - int(branch+2);
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//printf("---patching branch at 0x%08x to location 0x%08x (%d-0x%08x)\n", branch, target, offset, offset);
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// We have 2 words to work with here -- if offset is in range of a 24-bit
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// relative jump, emit that; otherwise, we do a pc-relative load into pc.
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if (-(1<<24) <= offset & offset < (1<<24)) {
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// ARM goodness, using unconditional B
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*branch = (NIns)( COND_AL | (0xA<<24) | ((offset >>2) & 0xFFFFFF) );
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} else {
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// LDR pc,[pc]
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*branch++ = (NIns)( COND_AL | (0x51<<20) | (PC<<16) | (PC<<12) | ( 0x004 ) );
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*branch = (NIns)target;
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}
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}
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RegisterMask Assembler::hint(LIns* i, RegisterMask allow /* = ~0 */)
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{
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uint32_t op = i->opcode();
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int prefer = ~0;
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if (op==LIR_call || op==LIR_fcall)
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prefer = rmask(R0);
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else if (op == LIR_callh)
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prefer = rmask(R1);
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else if (op == LIR_param)
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prefer = rmask(imm2register(i->imm8()));
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if (_allocator.free & allow & prefer)
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allow &= prefer;
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return allow;
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}
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void Assembler::asm_qjoin(LIns *ins)
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{
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int d = findMemFor(ins);
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AvmAssert(d);
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LIns* lo = ins->oprnd1();
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LIns* hi = ins->oprnd2();
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Register r = findRegFor(hi, GpRegs);
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ST(FP, d+4, r);
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// okay if r gets recycled.
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r = findRegFor(lo, GpRegs);
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ST(FP, d, r);
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freeRsrcOf(ins, false); // if we had a reg in use, emit a ST to flush it to mem
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}
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void Assembler::asm_store32(LIns *value, int dr, LIns *base)
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{
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// make sure what is in a register
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Reservation *rA, *rB;
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findRegFor2(GpRegs, value, rA, base, rB);
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Register ra = rA->reg;
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Register rb = rB->reg;
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ST(rb, dr, ra);
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}
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void Assembler::asm_restore(LInsp i, Reservation *resv, Register r)
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{
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(void)resv;
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int d = findMemFor(i);
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LD(r, d, FP);
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verbose_only(if (_verbose) {
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outputf(" restore %s",_thisfrag->lirbuf->names->formatRef(i));
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})
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}
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void Assembler::asm_spill(LInsp i, Reservation *resv, bool pop)
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{
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(void)i;
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(void)pop;
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if (resv->arIndex)
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{
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int d = disp(resv);
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// save to spill location
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Register rr = resv->reg;
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ST(FP, d, rr);
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verbose_only(if (_verbose){
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outputf(" spill %s",_thisfrag->lirbuf->names->formatRef(i));
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})
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}
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}
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void Assembler::asm_load64(LInsp ins)
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{
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LIns* base = ins->oprnd1();
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int db = ins->oprnd2()->constval();
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Reservation *resv = getresv(ins);
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int dr = disp(resv);
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NanoAssert(resv->reg == UnknownReg && dr != 0);
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Register rb = findRegFor(base, GpRegs);
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resv->reg = UnknownReg;
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asm_mmq(FP, dr, rb, db);
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freeRsrcOf(ins, false);
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}
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void Assembler::asm_store64(LInsp value, int dr, LInsp base)
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{
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int da = findMemFor(value);
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Register rb = findRegFor(base, GpRegs);
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asm_mmq(rb, dr, FP, da);
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}
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void Assembler::asm_quad(LInsp ins)
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{
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Reservation *rR = getresv(ins);
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int d = disp(rR);
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freeRsrcOf(ins, false);
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if (d)
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{
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const int32_t* p = (const int32_t*) (ins-2);
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STi(FP,d+4,p[1]);
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STi(FP,d,p[0]);
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}
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}
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bool Assembler::asm_qlo(LInsp ins, LInsp q)
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{
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(void)ins; (void)q;
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return false;
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}
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void Assembler::asm_nongp_copy(Register r, Register s)
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{
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// we will need this for VFP support
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(void)r; (void)s;
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NanoAssert(false);
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}
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Register Assembler::asm_binop_rhs_reg(LInsp ins)
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{
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return UnknownReg;
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}
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/**
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* copy 64 bits: (rd+dd) <- (rs+ds)
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*/
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void Assembler::asm_mmq(Register rd, int dd, Register rs, int ds)
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{
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// value is either a 64bit struct or maybe a float
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// that isn't live in an FPU reg. Either way, don't
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// put it in an FPU reg just to load & store it.
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// get a scratch reg
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Register t = registerAlloc(GpRegs & ~(rmask(rd)|rmask(rs)));
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_allocator.addFree(t);
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ST(rd, dd+4, t);
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LD(t, ds+4, rs);
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ST(rd, dd, t);
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LD(t, ds, rs);
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}
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void Assembler::asm_pusharg(LInsp p)
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{
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// arg goes on stack
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Reservation* rA = getresv(p);
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if (rA == 0)
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{
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Register ra = findRegFor(p, GpRegs);
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ST(SP,0,ra);
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}
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else if (rA->reg == UnknownReg)
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{
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ST(SP,0,Scratch);
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LD(Scratch,disp(rA),FP);
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}
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else
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{
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ST(SP,0,rA->reg);
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}
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}
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void Assembler::nativePageReset()
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{
|
||
|
_nSlot = 0;
|
||
|
_nExitSlot = 0;
|
||
|
}
|
||
|
|
||
|
void Assembler::nativePageSetup()
|
||
|
{
|
||
|
if (!_nIns) _nIns = pageAlloc();
|
||
|
if (!_nExitIns) _nExitIns = pageAlloc(true);
|
||
|
//fprintf(stderr, "assemble onto %x exits into %x\n", (int)_nIns, (int)_nExitIns);
|
||
|
|
||
|
if (!_nSlot)
|
||
|
{
|
||
|
// This needs to be done or the samepage macro gets confused; pageAlloc
|
||
|
// gives us a pointer to just past the end of the page.
|
||
|
_nIns--;
|
||
|
_nExitIns--;
|
||
|
|
||
|
// constpool starts at top of page and goes down,
|
||
|
// code starts at bottom of page and moves up
|
||
|
_nSlot = pageDataStart(_nIns); //(int*)(&((Page*)pageTop(_nIns))->lir[0]);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void Assembler::flushCache(NIns* n1, NIns* n2) {
|
||
|
#if defined(UNDER_CE)
|
||
|
// we changed the code, so we need to do this (sadly)
|
||
|
FlushInstructionCache(GetCurrentProcess(), NULL, NULL);
|
||
|
#elif defined(AVMPLUS_LINUX)
|
||
|
// Just need to clear this one page (not even the whole page really)
|
||
|
//Page *page = (Page*)pageTop(_nIns);
|
||
|
register unsigned long _beg __asm("a1") = (unsigned long)(n1);
|
||
|
register unsigned long _end __asm("a2") = (unsigned long)(n2);
|
||
|
register unsigned long _flg __asm("a3") = 0;
|
||
|
register unsigned long _swi __asm("r7") = 0xF0002;
|
||
|
__asm __volatile ("swi 0 @ sys_cacheflush" : "=r" (_beg) : "0" (_beg), "r" (_end), "r" (_flg), "r" (_swi));
|
||
|
#endif
|
||
|
}
|
||
|
|
||
|
NIns* Assembler::asm_adjustBranch(NIns* at, NIns* target)
|
||
|
{
|
||
|
// This always got emitted as a BL_far sequence; at points
|
||
|
// to the first of 4 instructions. Ensure that we're where
|
||
|
// we think we were..
|
||
|
NanoAssert(at[1] == (NIns)( COND_AL | OP_IMM | (1<<23) | (PC<<16) | (LR<<12) | (4) ));
|
||
|
NanoAssert(at[2] == (NIns)( COND_AL | (0x9<<21) | (0xFFF<<8) | (1<<4) | (IP) ));
|
||
|
|
||
|
NIns* was = (NIns*) at[3];
|
||
|
|
||
|
at[3] = (NIns)target;
|
||
|
|
||
|
flushCache(at, at+4);
|
||
|
|
||
|
#ifdef AVMPLUS_PORTING_API
|
||
|
NanoJIT_PortAPI_FlushInstructionCache(at, at+4);
|
||
|
#endif
|
||
|
|
||
|
return was;
|
||
|
}
|
||
|
|
||
|
void Assembler::underrunProtect(int bytes)
|
||
|
{
|
||
|
intptr_t u = bytes + sizeof(PageHeader)/sizeof(NIns) + 8;
|
||
|
if ( (samepage(_nIns,_nSlot) && (((intptr_t)_nIns-u) <= intptr_t(_nSlot+1))) ||
|
||
|
(!samepage((intptr_t)_nIns-u,_nIns)) )
|
||
|
{
|
||
|
NIns* target = _nIns;
|
||
|
|
||
|
_nIns = pageAlloc(_inExit);
|
||
|
|
||
|
// XXX _nIns at this point points to one past the end of
|
||
|
// the page, intended to be written into using *(--_nIns).
|
||
|
// However, (guess) something seems to be storing the value
|
||
|
// of _nIns as is, and then later generating a jump to a bogus
|
||
|
// address. So pre-decrement to ensure that it's always
|
||
|
// valid; we end up skipping using the last instruction this
|
||
|
// way.
|
||
|
_nIns--;
|
||
|
|
||
|
// Update slot, either to _nIns (if decremented above), or
|
||
|
// _nIns-1 once the above bug is fixed/found.
|
||
|
_nSlot = pageDataStart(_nIns);
|
||
|
|
||
|
// If samepage() is used on _nIns and _nSlot, it'll fail, since _nIns
|
||
|
// points to one past the end of the page right now. Assume that
|
||
|
// JMP_nochk won't ever try to write to _nSlot, and so won't ever
|
||
|
// check samepage(). See B_cond_chk macro.
|
||
|
JMP_nochk(target);
|
||
|
} else if (!_nSlot) {
|
||
|
// make sure that there's always a slot pointer
|
||
|
_nSlot = pageDataStart(_nIns);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void Assembler::BL_far(NIns* addr) {
|
||
|
// we have to stick an immediate into the stream and make lr
|
||
|
// point to the right spot before branching
|
||
|
underrunProtect(16);
|
||
|
|
||
|
// the address
|
||
|
*(--_nIns) = (NIns)((addr));
|
||
|
// bx ip // branch to the address we loaded earlier
|
||
|
*(--_nIns) = (NIns)( COND_AL | (0x9<<21) | (0xFFF<<8) | (1<<4) | (IP) );
|
||
|
// add lr, [pc + #4] // set lr to be past the address that we wrote
|
||
|
*(--_nIns) = (NIns)( COND_AL | OP_IMM | (1<<23) | (PC<<16) | (LR<<12) | (4) );
|
||
|
// ldr ip, [pc + #4] // load the address into ip, reading it from [pc+4]
|
||
|
*(--_nIns) = (NIns)( COND_AL | (0x59<<20) | (PC<<16) | (IP<<12) | (4));
|
||
|
asm_output1("bl %p (32-bit)", addr);
|
||
|
}
|
||
|
|
||
|
void Assembler::BL(NIns* addr) {
|
||
|
intptr_t offs = PC_OFFSET_FROM(addr,(intptr_t)_nIns-4);
|
||
|
if (JMP_S24_OFFSET_OK(offs)) {
|
||
|
// we can do this with a single BL call
|
||
|
underrunProtect(4);
|
||
|
*(--_nIns) = (NIns)( COND_AL | (0xB<<24) | (((offs)>>2) & 0xFFFFFF) ); \
|
||
|
asm_output1("bl %p", addr);
|
||
|
} else {
|
||
|
BL_far(addr);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
void Assembler::CALL(const CallInfo *ci)
|
||
|
{
|
||
|
intptr_t addr = ci->_address;
|
||
|
BL((NIns*)addr);
|
||
|
asm_output1(" (call %s)", ci->_name);
|
||
|
}
|
||
|
|
||
|
void Assembler::LD32_nochk(Register r, int32_t imm)
|
||
|
{
|
||
|
// We can always reach the const pool, since it's on the same page (<4096)
|
||
|
underrunProtect(8);
|
||
|
|
||
|
*(++_nSlot) = (int)imm;
|
||
|
|
||
|
//fprintf (stderr, "wrote slot(2) %p with %08x, jmp @ %p\n", _nSlot, (intptr_t)imm, _nIns-1);
|
||
|
|
||
|
int offset = PC_OFFSET_FROM(_nSlot,(intptr_t)(_nIns)-4);
|
||
|
|
||
|
NanoAssert(JMP_S24_OFFSET_OK(offset) && (offset < 0));
|
||
|
|
||
|
*(--_nIns) = (NIns)( COND_AL | (0x51<<20) | (PC<<16) | ((r)<<12) | ((-offset) & 0xFFFFFF) );
|
||
|
asm_output2("ld %s,%d",gpn(r),imm);
|
||
|
}
|
||
|
#endif /* FEATURE_NANOJIT */
|
||
|
}
|